Research and design of dual-field programmable length-scalable modular multiplier and adder
Modular multiplication, addition and subtraction are frequently used in ECC as the key operations. It has been an research hotspot that how to implement modular operations high-effciently and low-costly. Researching on Montgomery modular multiplication of FIOS, and modular add-sub, and combined with...
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| Format: | Article |
| Language: | zho |
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National Computer System Engineering Research Institute of China
2018-01-01
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| Series: | Dianzi Jishu Yingyong |
| Subjects: | |
| Online Access: | http://www.chinaaet.com/article/3000075911 |
| _version_ | 1818296451010134016 |
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| author | Li Jiamin Dai Zibin Wang Yiwei |
| author_facet | Li Jiamin Dai Zibin Wang Yiwei |
| author_sort | Li Jiamin |
| collection | DOAJ |
| description | Modular multiplication, addition and subtraction are frequently used in ECC as the key operations. It has been an research hotspot that how to implement modular operations high-effciently and low-costly. Researching on Montgomery modular multiplication of FIOS, and modular add-sub, and combined with reconfigurable technology, this paper implemented an length scalable MAS(multiplication-addition-subtraction) which support the operation in both finite field and prime field. This MAS is descript by Verilog HDL, and it was integrated in CMOS 0.18 μm technology library. Circuit maximum clock frequency is 230 MHz. This architecture not only has advantages in the speed and area, but also can flexibly achieve operations of different length. |
| first_indexed | 2024-12-13T04:03:44Z |
| format | Article |
| id | doaj.art-35ec9cf272f14006a42598b3b16c7de0 |
| institution | Directory Open Access Journal |
| issn | 0258-7998 |
| language | zho |
| last_indexed | 2024-12-13T04:03:44Z |
| publishDate | 2018-01-01 |
| publisher | National Computer System Engineering Research Institute of China |
| record_format | Article |
| series | Dianzi Jishu Yingyong |
| spelling | doaj.art-35ec9cf272f14006a42598b3b16c7de02022-12-22T00:00:19ZzhoNational Computer System Engineering Research Institute of ChinaDianzi Jishu Yingyong0258-79982018-01-01441283210.16157/j.issn.0258-7998.1721943000075911Research and design of dual-field programmable length-scalable modular multiplier and adderLi Jiamin0Dai Zibin1Wang Yiwei2Institute of Information Science and Technology of Zhengzhou，Zhengzhou 450001，ChinaInstitute of Information Science and Technology of Zhengzhou，Zhengzhou 450001，ChinaInstitute of Information Science and Technology of Zhengzhou，Zhengzhou 450001，ChinaModular multiplication, addition and subtraction are frequently used in ECC as the key operations. It has been an research hotspot that how to implement modular operations high-effciently and low-costly. Researching on Montgomery modular multiplication of FIOS, and modular add-sub, and combined with reconfigurable technology, this paper implemented an length scalable MAS(multiplication-addition-subtraction) which support the operation in both finite field and prime field. This MAS is descript by Verilog HDL, and it was integrated in CMOS 0.18 μm technology library. Circuit maximum clock frequency is 230 MHz. This architecture not only has advantages in the speed and area, but also can flexibly achieve operations of different length.http://www.chinaaet.com/article/3000075911length-scalabledual-field operationmultiplication-addition-subtractionpipeline |
| spellingShingle | Li Jiamin Dai Zibin Wang Yiwei Research and design of dual-field programmable length-scalable modular multiplier and adder Dianzi Jishu Yingyong length-scalable dual-field operation multiplication-addition-subtraction pipeline |
| title | Research and design of dual-field programmable length-scalable modular multiplier and adder |
| title_full | Research and design of dual-field programmable length-scalable modular multiplier and adder |
| title_fullStr | Research and design of dual-field programmable length-scalable modular multiplier and adder |
| title_full_unstemmed | Research and design of dual-field programmable length-scalable modular multiplier and adder |
| title_short | Research and design of dual-field programmable length-scalable modular multiplier and adder |
| title_sort | research and design of dual field programmable length scalable modular multiplier and adder |
| topic | length-scalable dual-field operation multiplication-addition-subtraction pipeline |
| url | http://www.chinaaet.com/article/3000075911 |
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