A secure SoC architecture design with dual DMA controllers
With the continuous advancement of System-on-Chip (SoC) technologies, the burgeoning data volumes emphasize the paramount importance of safeguarding data security and integrity. In this study, by leveraging Ascon in conjunction with enhancements to the SHA-1 algorithm, two secure Direct Memory Acces...
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
AIP Publishing LLC
2024-02-01
|
| Series: | AIP Advances |
| Online Access: | http://dx.doi.org/10.1063/5.0195148 |
| _version_ | 1797278268550807552 |
|---|---|
| author | Wei Wang Cong He Jiaqi Shi |
| author_facet | Wei Wang Cong He Jiaqi Shi |
| author_sort | Wei Wang |
| collection | DOAJ |
| description | With the continuous advancement of System-on-Chip (SoC) technologies, the burgeoning data volumes emphasize the paramount importance of safeguarding data security and integrity. In this study, by leveraging Ascon in conjunction with enhancements to the SHA-1 algorithm, two secure Direct Memory Access (DMA) controllers are designed to facilitate data encryption and comparison, respectively, culminating in the proposal of an SoC architecture featuring dual DMA controllers. Simulation outcomes demonstrate the system’s ability to achieve a maximum clock frequency of 120 MHz, offering a throughput rate of up to 3.2 GB/s. The multi-master multi-slave AHB bus matrix within the system operates impeccably, ensuring smooth functionality. Furthermore, the two DMA controllers exhibit independent operation, featuring flexible start-stop capabilities. Notably, they operate harmoniously without conflicts, optimizing the area utilization while adhering to a low power consumption design methodology. The results unequivocally affirm the feasibility of designing a secure SoC integrated with two DMA controllers. This hardware-based approach effectively ensures data security, showcasing promising prospects for real-world applications. |
| first_indexed | 2024-03-07T16:00:50Z |
| format | Article |
| id | doaj.art-36f32e4768dd402d938d9ee3a9f9024d |
| institution | Directory Open Access Journal |
| issn | 2158-3226 |
| language | English |
| last_indexed | 2024-03-07T16:00:50Z |
| publishDate | 2024-02-01 |
| publisher | AIP Publishing LLC |
| record_format | Article |
| series | AIP Advances |
| spelling | doaj.art-36f32e4768dd402d938d9ee3a9f9024d2024-03-04T21:29:33ZengAIP Publishing LLCAIP Advances2158-32262024-02-01142025125025125-1410.1063/5.0195148A secure SoC architecture design with dual DMA controllersWei Wang0Cong He1Jiaqi Shi2Jiangsu Province Engineering Research Center of Integrated Circuit Reliability Technology and Testing System, Wuxi University, Wuxi, ChinaSchool of Electronic and Information Engineering, Nanjing University of Information Science and Technology, Nanjing, ChinaSchool of Atmospheric Physics, Nanjing University of Information Science and Technology, Nanjing, ChinaWith the continuous advancement of System-on-Chip (SoC) technologies, the burgeoning data volumes emphasize the paramount importance of safeguarding data security and integrity. In this study, by leveraging Ascon in conjunction with enhancements to the SHA-1 algorithm, two secure Direct Memory Access (DMA) controllers are designed to facilitate data encryption and comparison, respectively, culminating in the proposal of an SoC architecture featuring dual DMA controllers. Simulation outcomes demonstrate the system’s ability to achieve a maximum clock frequency of 120 MHz, offering a throughput rate of up to 3.2 GB/s. The multi-master multi-slave AHB bus matrix within the system operates impeccably, ensuring smooth functionality. Furthermore, the two DMA controllers exhibit independent operation, featuring flexible start-stop capabilities. Notably, they operate harmoniously without conflicts, optimizing the area utilization while adhering to a low power consumption design methodology. The results unequivocally affirm the feasibility of designing a secure SoC integrated with two DMA controllers. This hardware-based approach effectively ensures data security, showcasing promising prospects for real-world applications.http://dx.doi.org/10.1063/5.0195148 |
| spellingShingle | Wei Wang Cong He Jiaqi Shi A secure SoC architecture design with dual DMA controllers AIP Advances |
| title | A secure SoC architecture design with dual DMA controllers |
| title_full | A secure SoC architecture design with dual DMA controllers |
| title_fullStr | A secure SoC architecture design with dual DMA controllers |
| title_full_unstemmed | A secure SoC architecture design with dual DMA controllers |
| title_short | A secure SoC architecture design with dual DMA controllers |
| title_sort | secure soc architecture design with dual dma controllers |
| url | http://dx.doi.org/10.1063/5.0195148 |
| work_keys_str_mv | AT weiwang asecuresocarchitecturedesignwithdualdmacontrollers AT conghe asecuresocarchitecturedesignwithdualdmacontrollers AT jiaqishi asecuresocarchitecturedesignwithdualdmacontrollers AT weiwang securesocarchitecturedesignwithdualdmacontrollers AT conghe securesocarchitecturedesignwithdualdmacontrollers AT jiaqishi securesocarchitecturedesignwithdualdmacontrollers |