Gate Engineering in SOI LDMOS for Device Reliability

Gate Engineering in SOI LDMOS for Device Reliability

A linearly graded doping drift region with step gate structure, used for improvement of reduced surface field (RESURF) SOI LDMOS transistor performance has been simulated with 0.35µm technology in this paper. The proposed device has one poly gate and double metal gate arranged in a stepped manner, f...

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Bibliographic Details
Main Authors:	Aanand, Sheu Gene, Imam Syed Sarwar, Lu Shao Wei, Aryadeep Chirag, Yang Shao Ming
Format:	Article
Language:	English
Published:	EDP Sciences 2016-01-01
Series:	MATEC Web of Conferences
Online Access:	http://dx.doi.org/10.1051/matecconf/20164402037

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