Analysing digital predistortion technique for computation‐efficient power amplifier linearisation in the presence of measurement noise
Abstract The noise is an inherent part of a transceiver system, which becomes more severe on low‐cost systems. The power amplifier (PA) further enhances this noise and the signal to be propagated to the receiver. The conventional approach of digital predistortion (DPD) assumes an ideal transceiver s...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2021-06-01
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| Series: | IET Science, Measurement & Technology |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/smt2.12041 |
| _version_ | 1798035569913102336 |
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| author | Girish Chandra Tripathi Meenakshi Rawat |
| author_facet | Girish Chandra Tripathi Meenakshi Rawat |
| author_sort | Girish Chandra Tripathi |
| collection | DOAJ |
| description | Abstract The noise is an inherent part of a transceiver system, which becomes more severe on low‐cost systems. The power amplifier (PA) further enhances this noise and the signal to be propagated to the receiver. The conventional approach of digital predistortion (DPD) assumes an ideal transceiver system while extracting data for the predistortion function generation. As a result, performance limitation arises due to residual signal–noise interaction. This study presents the accuracy and implementation issues of DPD on a low‐cost transceiver having lower bit resolution in the presence of transceiver noise. Different model architectures, as well as processing algorithms, are compared in terms of numerical stability of the solution (condition number of observation matrix), efficient field‐programmable gate array (FPGA) implementation (dispersion of coefficients, in‐band model performance (normalised mean square error), and out‐of‐band model performance (adjacent channel power ratio). The simulation results are tested on FPGA and direct conversion transceiver‐based platform using PA. A long‐term evolution signal with 64 quadrature amplitude modulation is used for performance evaluation. The suitability of the various polynomial models for fixed‐point implementation and the required memory size for implementing the DPD model is further established. |
| first_indexed | 2024-04-11T21:00:01Z |
| format | Article |
| id | doaj.art-38dfc277004446dcbdf7023c193c4ed5 |
| institution | Directory Open Access Journal |
| issn | 1751-8822 1751-8830 |
| language | English |
| last_indexed | 2024-04-11T21:00:01Z |
| publishDate | 2021-06-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Science, Measurement & Technology |
| spelling | doaj.art-38dfc277004446dcbdf7023c193c4ed52022-12-22T04:03:32ZengWileyIET Science, Measurement & Technology1751-88221751-88302021-06-0115439841010.1049/smt2.12041Analysing digital predistortion technique for computation‐efficient power amplifier linearisation in the presence of measurement noiseGirish Chandra Tripathi0Meenakshi Rawat1SDR Lab Department of Electronics and Communication Engineering Indian Institute of Technology Roorkee IndiaSDR Lab Department of Electronics and Communication Engineering Indian Institute of Technology Roorkee IndiaAbstract The noise is an inherent part of a transceiver system, which becomes more severe on low‐cost systems. The power amplifier (PA) further enhances this noise and the signal to be propagated to the receiver. The conventional approach of digital predistortion (DPD) assumes an ideal transceiver system while extracting data for the predistortion function generation. As a result, performance limitation arises due to residual signal–noise interaction. This study presents the accuracy and implementation issues of DPD on a low‐cost transceiver having lower bit resolution in the presence of transceiver noise. Different model architectures, as well as processing algorithms, are compared in terms of numerical stability of the solution (condition number of observation matrix), efficient field‐programmable gate array (FPGA) implementation (dispersion of coefficients, in‐band model performance (normalised mean square error), and out‐of‐band model performance (adjacent channel power ratio). The simulation results are tested on FPGA and direct conversion transceiver‐based platform using PA. A long‐term evolution signal with 64 quadrature amplitude modulation is used for performance evaluation. The suitability of the various polynomial models for fixed‐point implementation and the required memory size for implementing the DPD model is further established.https://doi.org/10.1049/smt2.12041AmplifiersLogic circuitsModulation and coding methodsMobile radio systemsInterpolation and function approximation (numerical analysis) |
| spellingShingle | Girish Chandra Tripathi Meenakshi Rawat Analysing digital predistortion technique for computation‐efficient power amplifier linearisation in the presence of measurement noise IET Science, Measurement & Technology Amplifiers Logic circuits Modulation and coding methods Mobile radio systems Interpolation and function approximation (numerical analysis) |
| title | Analysing digital predistortion technique for computation‐efficient power amplifier linearisation in the presence of measurement noise |
| title_full | Analysing digital predistortion technique for computation‐efficient power amplifier linearisation in the presence of measurement noise |
| title_fullStr | Analysing digital predistortion technique for computation‐efficient power amplifier linearisation in the presence of measurement noise |
| title_full_unstemmed | Analysing digital predistortion technique for computation‐efficient power amplifier linearisation in the presence of measurement noise |
| title_short | Analysing digital predistortion technique for computation‐efficient power amplifier linearisation in the presence of measurement noise |
| title_sort | analysing digital predistortion technique for computation efficient power amplifier linearisation in the presence of measurement noise |
| topic | Amplifiers Logic circuits Modulation and coding methods Mobile radio systems Interpolation and function approximation (numerical analysis) |
| url | https://doi.org/10.1049/smt2.12041 |
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