Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices
Achieving low-cost and high-performance network security communication is necessary for Internet of Things (IoT) devices, including intelligent sensors and mobile robots. Designing hardware accelerators to accelerate multiple computationally intensive cryptographic primitives in various network secu...
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-11-01
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| Series: | Sensors |
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| Online Access: | https://www.mdpi.com/1424-8220/22/23/9160 |
| _version_ | 1797462168187174912 |
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| author | Xvpeng Zhang Bingqiang Liu Yaqi Zhao Xiaoyu Hu Zixuan Shen Zhaoxia Zheng Zhenglin Liu Kwen-Siong Chong Guoyi Yu Chao Wang Xuecheng Zou |
| author_facet | Xvpeng Zhang Bingqiang Liu Yaqi Zhao Xiaoyu Hu Zixuan Shen Zhaoxia Zheng Zhenglin Liu Kwen-Siong Chong Guoyi Yu Chao Wang Xuecheng Zou |
| author_sort | Xvpeng Zhang |
| collection | DOAJ |
| description | Achieving low-cost and high-performance network security communication is necessary for Internet of Things (IoT) devices, including intelligent sensors and mobile robots. Designing hardware accelerators to accelerate multiple computationally intensive cryptographic primitives in various network security protocols is challenging. Different from existing unified reconfigurable cryptographic accelerators with relatively low efficiency and high latency, this paper presents design and analysis of a reconfigurable cryptographic accelerator consisting of a reconfigurable cipher unit and a reconfigurable hash unit to support widely used cryptographic algorithms for IoT Devices, which require block ciphers and hash functions simultaneously. Based on a detailed and comprehensive algorithmic analysis of both the block ciphers and hash functions in terms of basic algorithm structures and common cryptographic operators, the proposed reconfigurable cryptographic accelerator is designed by reusing key register files and operators to build unified data paths. Both the reconfigurable cipher unit and the reconfigurable hash unit contain a unified data path to implement Data Encryption Standard (DES)/Advanced Encryption Standard (AES)/ShangMi 4 (SM4) and Secure Hash Algorithm-1 (SHA-1)/SHA-256/SM3 algorithms, respectively. A reconfigurable S-Box for AES and SM4 is designed based on the composite field Galois field (GF) GF(((2<sup>2</sup>)<sup>2</sup>)<sup>2</sup>), which significantly reduces hardware overhead and power consumption compared with the conventional implementation by look-up tables. The experimental results based on 65-nm application-specific integrated circuit (ASIC) implementation show that the achieved energy efficiency and area efficiency of the proposed design is 441 Gbps/W and 37.55 Gbps/mm<sup>2</sup>, respectively, which is suitable for IoT devices with limited battery and form factor. The result of delay analysis also shows that the number of delay cycles of our design can be reduced by 83% compared with the state-of-the-art design, which shows that the proposed design is more suitable for applications including 5G/Wi-Fi/ZigBee/Ethernet network standards to accelerate block ciphers and hash functions simultaneously. |
| first_indexed | 2024-03-09T17:32:40Z |
| format | Article |
| id | doaj.art-39691db0aa8a4962a268ecd31b543a06 |
| institution | Directory Open Access Journal |
| issn | 1424-8220 |
| language | English |
| last_indexed | 2024-03-09T17:32:40Z |
| publishDate | 2022-11-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Sensors |
| spelling | doaj.art-39691db0aa8a4962a268ecd31b543a062023-11-24T12:09:31ZengMDPI AGSensors1424-82202022-11-012223916010.3390/s22239160Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT DevicesXvpeng Zhang0Bingqiang Liu1Yaqi Zhao2Xiaoyu Hu3Zixuan Shen4Zhaoxia Zheng5Zhenglin Liu6Kwen-Siong Chong7Guoyi Yu8Chao Wang9Xuecheng Zou10School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, ChinaSchool of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, ChinaSchool of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, ChinaSchool of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, ChinaSchool of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, ChinaSchool of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, ChinaSchool of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, ChinaTemasek Laboratories, Nanyang Technological University, Singapore 639798, SingaporeSchool of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, ChinaSchool of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, ChinaSchool of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, ChinaAchieving low-cost and high-performance network security communication is necessary for Internet of Things (IoT) devices, including intelligent sensors and mobile robots. Designing hardware accelerators to accelerate multiple computationally intensive cryptographic primitives in various network security protocols is challenging. Different from existing unified reconfigurable cryptographic accelerators with relatively low efficiency and high latency, this paper presents design and analysis of a reconfigurable cryptographic accelerator consisting of a reconfigurable cipher unit and a reconfigurable hash unit to support widely used cryptographic algorithms for IoT Devices, which require block ciphers and hash functions simultaneously. Based on a detailed and comprehensive algorithmic analysis of both the block ciphers and hash functions in terms of basic algorithm structures and common cryptographic operators, the proposed reconfigurable cryptographic accelerator is designed by reusing key register files and operators to build unified data paths. Both the reconfigurable cipher unit and the reconfigurable hash unit contain a unified data path to implement Data Encryption Standard (DES)/Advanced Encryption Standard (AES)/ShangMi 4 (SM4) and Secure Hash Algorithm-1 (SHA-1)/SHA-256/SM3 algorithms, respectively. A reconfigurable S-Box for AES and SM4 is designed based on the composite field Galois field (GF) GF(((2<sup>2</sup>)<sup>2</sup>)<sup>2</sup>), which significantly reduces hardware overhead and power consumption compared with the conventional implementation by look-up tables. The experimental results based on 65-nm application-specific integrated circuit (ASIC) implementation show that the achieved energy efficiency and area efficiency of the proposed design is 441 Gbps/W and 37.55 Gbps/mm<sup>2</sup>, respectively, which is suitable for IoT devices with limited battery and form factor. The result of delay analysis also shows that the number of delay cycles of our design can be reduced by 83% compared with the state-of-the-art design, which shows that the proposed design is more suitable for applications including 5G/Wi-Fi/ZigBee/Ethernet network standards to accelerate block ciphers and hash functions simultaneously.https://www.mdpi.com/1424-8220/22/23/9160reconfigurable cryptographic acceleratorhardware securityintelligent sensors and mobile robotsintelligent Internet of Things |
| spellingShingle | Xvpeng Zhang Bingqiang Liu Yaqi Zhao Xiaoyu Hu Zixuan Shen Zhaoxia Zheng Zhenglin Liu Kwen-Siong Chong Guoyi Yu Chao Wang Xuecheng Zou Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices Sensors reconfigurable cryptographic accelerator hardware security intelligent sensors and mobile robots intelligent Internet of Things |
| title | Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices |
| title_full | Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices |
| title_fullStr | Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices |
| title_full_unstemmed | Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices |
| title_short | Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices |
| title_sort | design and analysis of area and energy efficient reconfigurable cryptographic accelerator for securing iot devices |
| topic | reconfigurable cryptographic accelerator hardware security intelligent sensors and mobile robots intelligent Internet of Things |
| url | https://www.mdpi.com/1424-8220/22/23/9160 |
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