Efficient and Scalable FPGA-Oriented Design of QC-LDPC Bit-Flipping Decoders for Post-Quantum Cryptography
Considering code-based cryptography, quasi-cyclic low-density parity-check (QC-LDPC) codes are foreseen as one of the few solutions to design post-quantum cryptosystems. The bit-flipping algorithm is at the core of the decoding procedure of such codes when used to design cryptosystems. An effective...
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| Format: | Article |
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IEEE
2020-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/9180360/ |
| _version_ | 1818430554359463936 |
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| author | Davide Zoni Andrea Galimberti William Fornaciari |
| author_facet | Davide Zoni Andrea Galimberti William Fornaciari |
| author_sort | Davide Zoni |
| collection | DOAJ |
| description | Considering code-based cryptography, quasi-cyclic low-density parity-check (QC-LDPC) codes are foreseen as one of the few solutions to design post-quantum cryptosystems. The bit-flipping algorithm is at the core of the decoding procedure of such codes when used to design cryptosystems. An effective design must account for the computational complexity of the decoding and the code size required to ensure the security margin against attacks led by quantum computers. To this end, it is of paramount importance to deliver efficient and flexible hardware implementations to support quantum-resistant public-key cryptosystems, since available software solutions cannot cope with the required performance. This manuscript proposes an efficient and scalable architecture for the implementation of the bit-flipping procedure targeting large QC-LDPC codes for post-quantum cryptography. To demonstrate the effectiveness of our solution, we employed the nine configurations of the LEDAcrypt cryptosystem as representative use cases for QC-LDPC codes suitable for post-quantum cryptography. For each configuration, our template architecture can deliver a performance-optimized decoder implementation for all the FPGAs of the Xilinx Artix-7 mid-range family. The experimental results demonstrate that our optimized architecture allows the implementation of large QC-LDPC codes even on the smallest FPGA of the Xilinx Artix-7 family. Considering the implementation of our decoder on the Xilinx Artix-7 200 FPGA, the experimental results show an average performance speedup of 5 times across all the LEDAcrypt configurations, compared to the official optimized software implementation of the decoder that employs the Intel AVX2 extension. |
| first_indexed | 2024-12-14T15:35:15Z |
| format | Article |
| id | doaj.art-3b2c253a9b97485f952d4b995029dc29 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-14T15:35:15Z |
| publishDate | 2020-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-3b2c253a9b97485f952d4b995029dc292022-12-21T22:55:44ZengIEEEIEEE Access2169-35362020-01-01816341916343310.1109/ACCESS.2020.30202629180360Efficient and Scalable FPGA-Oriented Design of QC-LDPC Bit-Flipping Decoders for Post-Quantum CryptographyDavide Zoni0https://orcid.org/0000-0002-9951-062XAndrea Galimberti1William Fornaciari2https://orcid.org/0000-0001-8294-730XDipartimento di Elettronica Informazione e Bioingegneria (DEIB), Politecnico di Milano, Milan, ItalyDipartimento di Elettronica Informazione e Bioingegneria (DEIB), Politecnico di Milano, Milan, ItalyDipartimento di Elettronica Informazione e Bioingegneria (DEIB), Politecnico di Milano, Milan, ItalyConsidering code-based cryptography, quasi-cyclic low-density parity-check (QC-LDPC) codes are foreseen as one of the few solutions to design post-quantum cryptosystems. The bit-flipping algorithm is at the core of the decoding procedure of such codes when used to design cryptosystems. An effective design must account for the computational complexity of the decoding and the code size required to ensure the security margin against attacks led by quantum computers. To this end, it is of paramount importance to deliver efficient and flexible hardware implementations to support quantum-resistant public-key cryptosystems, since available software solutions cannot cope with the required performance. This manuscript proposes an efficient and scalable architecture for the implementation of the bit-flipping procedure targeting large QC-LDPC codes for post-quantum cryptography. To demonstrate the effectiveness of our solution, we employed the nine configurations of the LEDAcrypt cryptosystem as representative use cases for QC-LDPC codes suitable for post-quantum cryptography. For each configuration, our template architecture can deliver a performance-optimized decoder implementation for all the FPGAs of the Xilinx Artix-7 mid-range family. The experimental results demonstrate that our optimized architecture allows the implementation of large QC-LDPC codes even on the smallest FPGA of the Xilinx Artix-7 family. Considering the implementation of our decoder on the Xilinx Artix-7 200 FPGA, the experimental results show an average performance speedup of 5 times across all the LEDAcrypt configurations, compared to the official optimized software implementation of the decoder that employs the Intel AVX2 extension.https://ieeexplore.ieee.org/document/9180360/QC-LDPC codesbit-flipping decodingcode-based cryptographypost-quantum cryptographyapplied cryptographyFPGA |
| spellingShingle | Davide Zoni Andrea Galimberti William Fornaciari Efficient and Scalable FPGA-Oriented Design of QC-LDPC Bit-Flipping Decoders for Post-Quantum Cryptography IEEE Access QC-LDPC codes bit-flipping decoding code-based cryptography post-quantum cryptography applied cryptography FPGA |
| title | Efficient and Scalable FPGA-Oriented Design of QC-LDPC Bit-Flipping Decoders for Post-Quantum Cryptography |
| title_full | Efficient and Scalable FPGA-Oriented Design of QC-LDPC Bit-Flipping Decoders for Post-Quantum Cryptography |
| title_fullStr | Efficient and Scalable FPGA-Oriented Design of QC-LDPC Bit-Flipping Decoders for Post-Quantum Cryptography |
| title_full_unstemmed | Efficient and Scalable FPGA-Oriented Design of QC-LDPC Bit-Flipping Decoders for Post-Quantum Cryptography |
| title_short | Efficient and Scalable FPGA-Oriented Design of QC-LDPC Bit-Flipping Decoders for Post-Quantum Cryptography |
| title_sort | efficient and scalable fpga oriented design of qc ldpc bit flipping decoders for post quantum cryptography |
| topic | QC-LDPC codes bit-flipping decoding code-based cryptography post-quantum cryptography applied cryptography FPGA |
| url | https://ieeexplore.ieee.org/document/9180360/ |
| work_keys_str_mv | AT davidezoni efficientandscalablefpgaorienteddesignofqcldpcbitflippingdecodersforpostquantumcryptography AT andreagalimberti efficientandscalablefpgaorienteddesignofqcldpcbitflippingdecodersforpostquantumcryptography AT williamfornaciari efficientandscalablefpgaorienteddesignofqcldpcbitflippingdecodersforpostquantumcryptography |