ARCHITECTURAL AND STRUCTURAL AND FUNCTIONAL FEATURES OF THE ORGANIZATION OF PARALLEL-HIERARCHICAL MEMORY
Parallel hierarchical memory (PI memory) is a new type of memory that is designed to improve the performance of parallel computing systems. PI memory is composed of two blocks: a mask RAM and a tail element RAM. The mask RAM stores the masks that are used to encode the information, while the tail e...
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| Format: | Article |
| Language: | English |
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Lublin University of Technology
2024-03-01
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| Series: | Informatyka, Automatyka, Pomiary w Gospodarce i Ochronie Środowiska |
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| Online Access: | https://ph.pollub.pl/index.php/iapgos/article/view/5615 |
| _version_ | 1797233884836921344 |
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| author | Leonid Timchenko Natalia Kokriatska Volodymyr Tverdomed Iryna Yepifanova Yurii Didenko Dmytro Zhuk Maksym Kozyr Iryna Shakhina |
| author_facet | Leonid Timchenko Natalia Kokriatska Volodymyr Tverdomed Iryna Yepifanova Yurii Didenko Dmytro Zhuk Maksym Kozyr Iryna Shakhina |
| author_sort | Leonid Timchenko |
| collection | DOAJ |
| description |
Parallel hierarchical memory (PI memory) is a new type of memory that is designed to improve the performance of parallel computing systems. PI memory is composed of two blocks: a mask RAM and a tail element RAM. The mask RAM stores the masks that are used to encode the information, while the tail element RAM stores the actual information. The address block of the PI memory is responsible for generating the physical addresses of the cells where the tail elements and their masks are stored. The address block also stores the field of addresses where the array was written and associates this field of addresses with the corresponding external address used to write the array. The proposed address block structure is able to efficiently generate the physical addresses of the cells where the tail elements and their masks are stored. The address block is also able to store the field of addresses where the array was written and associate this field of addresses with the corresponding external address used to write the array. The proposed address block structure has been implemented in a prototype PI memory. The prototype PI memory has been shown to be able to achieve significant performance improvements over traditional memory architectures. The paper will present a detailed description of the PI transformation algorithm, a description of the different modes of addressing organization that can be used in PI memory, an analysis of the efficiency of parallel-hierarchical memory structures, and a discussion of the challenges and future research directions in the field of PI memory.
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| first_indexed | 2024-04-24T16:23:16Z |
| format | Article |
| id | doaj.art-3c16202022e347d6b47c52b47a3a1f10 |
| institution | Directory Open Access Journal |
| issn | 2083-0157 2391-6761 |
| language | English |
| last_indexed | 2024-04-24T16:23:16Z |
| publishDate | 2024-03-01 |
| publisher | Lublin University of Technology |
| record_format | Article |
| series | Informatyka, Automatyka, Pomiary w Gospodarce i Ochronie Środowiska |
| spelling | doaj.art-3c16202022e347d6b47c52b47a3a1f102024-03-31T08:19:57ZengLublin University of TechnologyInformatyka, Automatyka, Pomiary w Gospodarce i Ochronie Środowiska2083-01572391-67612024-03-0114110.35784/iapgos.5615ARCHITECTURAL AND STRUCTURAL AND FUNCTIONAL FEATURES OF THE ORGANIZATION OF PARALLEL-HIERARCHICAL MEMORYLeonid Timchenko0https://orcid.org/0000-0001-5056-5913Natalia Kokriatska1https://orcid.org/0000-0003-0090-3886Volodymyr Tverdomed2https://orcid.org/0000-0002-0695-1304Iryna Yepifanova3https://orcid.org/0000-0002-0391-9026Yurii Didenko4https://orcid.org/0009-0008-1033-4238Dmytro Zhuk5https://orcid.org/0000-0001-8951-5542Maksym Kozyr6https://orcid.org/0009-0007-2564-6552Iryna Shakhina7https://orcid.org/0000-0002-4318-6189State University of Infrastructure and TechnologyState University of Infrastructure and TechnologyState University of Infrastructure and TechnologyVinnytsia National Technical UnіversityState University of Infrastructure and TechnologyState University of Infrastructure and Technology, Kyiv, UkraineState University of Infrastructure and TechnologyVinnytsia Mykhailo Kotsiubynskyi State Pedagogical University Parallel hierarchical memory (PI memory) is a new type of memory that is designed to improve the performance of parallel computing systems. PI memory is composed of two blocks: a mask RAM and a tail element RAM. The mask RAM stores the masks that are used to encode the information, while the tail element RAM stores the actual information. The address block of the PI memory is responsible for generating the physical addresses of the cells where the tail elements and their masks are stored. The address block also stores the field of addresses where the array was written and associates this field of addresses with the corresponding external address used to write the array. The proposed address block structure is able to efficiently generate the physical addresses of the cells where the tail elements and their masks are stored. The address block is also able to store the field of addresses where the array was written and associate this field of addresses with the corresponding external address used to write the array. The proposed address block structure has been implemented in a prototype PI memory. The prototype PI memory has been shown to be able to achieve significant performance improvements over traditional memory architectures. The paper will present a detailed description of the PI transformation algorithm, a description of the different modes of addressing organization that can be used in PI memory, an analysis of the efficiency of parallel-hierarchical memory structures, and a discussion of the challenges and future research directions in the field of PI memory. https://ph.pollub.pl/index.php/iapgos/article/view/5615parallel hierarchical memoryPI memoryaddress blockmask RAMtail element RAMperformance improvement |
| spellingShingle | Leonid Timchenko Natalia Kokriatska Volodymyr Tverdomed Iryna Yepifanova Yurii Didenko Dmytro Zhuk Maksym Kozyr Iryna Shakhina ARCHITECTURAL AND STRUCTURAL AND FUNCTIONAL FEATURES OF THE ORGANIZATION OF PARALLEL-HIERARCHICAL MEMORY Informatyka, Automatyka, Pomiary w Gospodarce i Ochronie Środowiska parallel hierarchical memory PI memory address block mask RAM tail element RAM performance improvement |
| title | ARCHITECTURAL AND STRUCTURAL AND FUNCTIONAL FEATURES OF THE ORGANIZATION OF PARALLEL-HIERARCHICAL MEMORY |
| title_full | ARCHITECTURAL AND STRUCTURAL AND FUNCTIONAL FEATURES OF THE ORGANIZATION OF PARALLEL-HIERARCHICAL MEMORY |
| title_fullStr | ARCHITECTURAL AND STRUCTURAL AND FUNCTIONAL FEATURES OF THE ORGANIZATION OF PARALLEL-HIERARCHICAL MEMORY |
| title_full_unstemmed | ARCHITECTURAL AND STRUCTURAL AND FUNCTIONAL FEATURES OF THE ORGANIZATION OF PARALLEL-HIERARCHICAL MEMORY |
| title_short | ARCHITECTURAL AND STRUCTURAL AND FUNCTIONAL FEATURES OF THE ORGANIZATION OF PARALLEL-HIERARCHICAL MEMORY |
| title_sort | architectural and structural and functional features of the organization of parallel hierarchical memory |
| topic | parallel hierarchical memory PI memory address block mask RAM tail element RAM performance improvement |
| url | https://ph.pollub.pl/index.php/iapgos/article/view/5615 |
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