Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2m)
Abstract This article offers a new bit‐serial systolic array architecture to implement the interleaved multiplication algorithm in the binary‐extended field. The exhibited multiplier structure is more proper for VLSI implementation as it has regular cell structures as well as local communication wir...
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| Format: | Article |
| Language: | English |
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Hindawi-IET
2021-05-01
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| Series: | IET Computers & Digital Techniques |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/cdt2.12026 |
| _version_ | 1797422626112536576 |
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| author | Atef Ibrahim |
| author_facet | Atef Ibrahim |
| author_sort | Atef Ibrahim |
| collection | DOAJ |
| description | Abstract This article offers a new bit‐serial systolic array architecture to implement the interleaved multiplication algorithm in the binary‐extended field. The exhibited multiplier structure is more proper for VLSI implementation as it has regular cell structures as well as local communication wires between the cells. The ASIC implementation results of the suggested bit‐serial multiplier structure and the existing competitive bit‐serial multiplier structures previously described in the literature indicate that the recommended design achieves a notable reduction in area and significant improvement of area‐time complexities by at least 28.4% and 35.7%, respectively. Therefore, it is more proper for cryptographic applications forcing more restrictions on the space. |
| first_indexed | 2024-03-09T07:36:06Z |
| format | Article |
| id | doaj.art-3c3edbb509ed4e45af2b63e2f9a3df06 |
| institution | Directory Open Access Journal |
| issn | 1751-8601 1751-861X |
| language | English |
| last_indexed | 2024-03-09T07:36:06Z |
| publishDate | 2021-05-01 |
| publisher | Hindawi-IET |
| record_format | Article |
| series | IET Computers & Digital Techniques |
| spelling | doaj.art-3c3edbb509ed4e45af2b63e2f9a3df062023-12-03T05:39:35ZengHindawi-IETIET Computers & Digital Techniques1751-86011751-861X2021-05-0115322322910.1049/cdt2.12026Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2m)Atef Ibrahim0Computer Engineering Department College of Computer Engineering and Sciences Prince Sattam Bin Abdulaziz University Al‐Kharj Saudi ArabiaAbstract This article offers a new bit‐serial systolic array architecture to implement the interleaved multiplication algorithm in the binary‐extended field. The exhibited multiplier structure is more proper for VLSI implementation as it has regular cell structures as well as local communication wires between the cells. The ASIC implementation results of the suggested bit‐serial multiplier structure and the existing competitive bit‐serial multiplier structures previously described in the literature indicate that the recommended design achieves a notable reduction in area and significant improvement of area‐time complexities by at least 28.4% and 35.7%, respectively. Therefore, it is more proper for cryptographic applications forcing more restrictions on the space.https://doi.org/10.1049/cdt2.12026application specific integrated circuitscomputational complexitycryptographydigital arithmeticGalois fieldsmultiplying circuits |
| spellingShingle | Atef Ibrahim Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2m) IET Computers & Digital Techniques application specific integrated circuits computational complexity cryptography digital arithmetic Galois fields multiplying circuits |
| title | Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2m) |
| title_full | Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2m) |
| title_fullStr | Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2m) |
| title_full_unstemmed | Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2m) |
| title_short | Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2m) |
| title_sort | low space bit serial systolic array architecture for interleaved multiplication over gf 2m |
| topic | application specific integrated circuits computational complexity cryptography digital arithmetic Galois fields multiplying circuits |
| url | https://doi.org/10.1049/cdt2.12026 |
| work_keys_str_mv | AT atefibrahim lowspacebitserialsystolicarrayarchitectureforinterleavedmultiplicationovergf2m |