Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2m)
Abstract This article offers a new bit‐serial systolic array architecture to implement the interleaved multiplication algorithm in the binary‐extended field. The exhibited multiplier structure is more proper for VLSI implementation as it has regular cell structures as well as local communication wir...
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| Format: | Article |
| Language: | English |
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Hindawi-IET
2021-05-01
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| Series: | IET Computers & Digital Techniques |
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| Online Access: | https://doi.org/10.1049/cdt2.12026 |