A Tunable Foreground Self-Calibration Scheme for Split Successive-Approximation Register Analog-to-Digital Converter
The capacitor mismatch among diverse defects caused by variations in the manufacturing process significantly affects the linearity of the capacitor array used to implement the capacitive digital-to-analog converter (CDAC) in the successive-approximation register (SAR) analog-to-digital converter (AD...
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MDPI AG
2024-02-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/13/4/755 |
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| author | Joonsung Park Jiwon Lee Jacob A. Abraham Byoungho Kim |
| author_facet | Joonsung Park Jiwon Lee Jacob A. Abraham Byoungho Kim |
| author_sort | Joonsung Park |
| collection | DOAJ |
| description | The capacitor mismatch among diverse defects caused by variations in the manufacturing process significantly affects the linearity of the capacitor array used to implement the capacitive digital-to-analog converter (CDAC) in the successive-approximation register (SAR) analog-to-digital converter (ADC). Accordingly, the linearity of the SAR ADC is limited by that of capacitor array, resulting in serious yield loss. This paper proposes an efficient foreground self-calibration technique to enhance the linearity of the SAR ADCs by mitigating the capacitor mismatch based on the split ADC architecture along with variable capacitors. In this work, two ADC channels (i.e., ADC1 and ADC2) for the split ADC architecture include their capacitive DACs (CDACs) whose binary-weighted capacitor arrays consist of variable capacitors. A charge-sharing SAR ADC is used for each ADC channel. In the normal operation mode, their digital outputs are averaged to be the final ADC output, as in a conventional split ADC. In the calibration mode, every single binary-weighted capacitor for the two ADCs is sequentially calibrated by making parallel or/and antiparallel connection among two or thee capacitors from the two channels. For instance, because the capacitors of the CDACs ideally exhibit the binary-weighted relation as <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><msub><mi>C</mi><mi>n</mi></msub><mo>=</mo><mn>2</mn><mo>×</mo><msub><mi>C</mi><mrow><mi>n</mi><mo>−</mo><mn>1</mn></mrow></msub></mrow></semantics></math></inline-formula>, the variable capacitor <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi>C</mi><mi>n</mi></msub></semantics></math></inline-formula> of ADC1 can be updated to be closest to the sum of <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi>C</mi><mrow><mi>n</mi><mo>−</mo><mn>1</mn></mrow></msub></semantics></math></inline-formula> of ADC1 and <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi>C</mi><mrow><mi>n</mi><mo>−</mo><mn>1</mn></mrow></msub></semantics></math></inline-formula> of ADC2 for the calibration. For the process, the two capacitor arrays of the two ADCs can be reconfigured to be connected to each other, so that the <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi>C</mi><mi>n</mi></msub></semantics></math></inline-formula> of ADC1 can be connected with two of the <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi>C</mi><mrow><mi>n</mi><mo>−</mo><mn>1</mn></mrow></msub></semantics></math></inline-formula> of ADC1 and ADC2 in antiparallel. The two voltages at the top and the bottom plates of the CDAC are compared by a comparator of ADC1, and the comparison results are used to update <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi>C</mi><mi>n</mi></msub></semantics></math></inline-formula>. This process is iterated, until <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi>C</mi><mi>n</mi></msub></semantics></math></inline-formula> is in agreement with the sum of two of <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi>C</mi><mrow><mi>n</mi><mo>−</mo><mn>1</mn></mrow></msub></semantics></math></inline-formula>. Finally, all the capacitors can be calibrated in this way to have the binary-weighted relation. The simulation results based on the proposed work with a split SAR ADC model verified that the proposed technique can be practically used, by showing that the total harmonic distortion and the signal-to-noise-and-distortion ratio were enhanced by <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mn>21.8</mn></mrow></semantics></math></inline-formula> dB and <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mn>6.4</mn></mrow></semantics></math></inline-formula> dB, respectively. |
| first_indexed | 2024-03-07T22:34:22Z |
| format | Article |
| id | doaj.art-3c657e9561204f1fbb0c959462a0ef3c |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-07T22:34:22Z |
| publishDate | 2024-02-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-3c657e9561204f1fbb0c959462a0ef3c2024-02-23T15:14:50ZengMDPI AGElectronics2079-92922024-02-0113475510.3390/electronics13040755A Tunable Foreground Self-Calibration Scheme for Split Successive-Approximation Register Analog-to-Digital ConverterJoonsung Park0Jiwon Lee1Jacob A. Abraham2Byoungho Kim3Division of Electrical Engineering, Hanyang University, Ansan 15588, Republic of KoreaDivision of Electrical Engineering, Hanyang University, Ansan 15588, Republic of KoreaDepartment of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX 78712, USADivision of Electrical Engineering, Hanyang University, Ansan 15588, Republic of KoreaThe capacitor mismatch among diverse defects caused by variations in the manufacturing process significantly affects the linearity of the capacitor array used to implement the capacitive digital-to-analog converter (CDAC) in the successive-approximation register (SAR) analog-to-digital converter (ADC). Accordingly, the linearity of the SAR ADC is limited by that of capacitor array, resulting in serious yield loss. This paper proposes an efficient foreground self-calibration technique to enhance the linearity of the SAR ADCs by mitigating the capacitor mismatch based on the split ADC architecture along with variable capacitors. In this work, two ADC channels (i.e., ADC1 and ADC2) for the split ADC architecture include their capacitive DACs (CDACs) whose binary-weighted capacitor arrays consist of variable capacitors. A charge-sharing SAR ADC is used for each ADC channel. In the normal operation mode, their digital outputs are averaged to be the final ADC output, as in a conventional split ADC. In the calibration mode, every single binary-weighted capacitor for the two ADCs is sequentially calibrated by making parallel or/and antiparallel connection among two or thee capacitors from the two channels. For instance, because the capacitors of the CDACs ideally exhibit the binary-weighted relation as <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><msub><mi>C</mi><mi>n</mi></msub><mo>=</mo><mn>2</mn><mo>×</mo><msub><mi>C</mi><mrow><mi>n</mi><mo>−</mo><mn>1</mn></mrow></msub></mrow></semantics></math></inline-formula>, the variable capacitor <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi>C</mi><mi>n</mi></msub></semantics></math></inline-formula> of ADC1 can be updated to be closest to the sum of <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi>C</mi><mrow><mi>n</mi><mo>−</mo><mn>1</mn></mrow></msub></semantics></math></inline-formula> of ADC1 and <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi>C</mi><mrow><mi>n</mi><mo>−</mo><mn>1</mn></mrow></msub></semantics></math></inline-formula> of ADC2 for the calibration. For the process, the two capacitor arrays of the two ADCs can be reconfigured to be connected to each other, so that the <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi>C</mi><mi>n</mi></msub></semantics></math></inline-formula> of ADC1 can be connected with two of the <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi>C</mi><mrow><mi>n</mi><mo>−</mo><mn>1</mn></mrow></msub></semantics></math></inline-formula> of ADC1 and ADC2 in antiparallel. The two voltages at the top and the bottom plates of the CDAC are compared by a comparator of ADC1, and the comparison results are used to update <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi>C</mi><mi>n</mi></msub></semantics></math></inline-formula>. This process is iterated, until <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi>C</mi><mi>n</mi></msub></semantics></math></inline-formula> is in agreement with the sum of two of <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi>C</mi><mrow><mi>n</mi><mo>−</mo><mn>1</mn></mrow></msub></semantics></math></inline-formula>. Finally, all the capacitors can be calibrated in this way to have the binary-weighted relation. The simulation results based on the proposed work with a split SAR ADC model verified that the proposed technique can be practically used, by showing that the total harmonic distortion and the signal-to-noise-and-distortion ratio were enhanced by <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mn>21.8</mn></mrow></semantics></math></inline-formula> dB and <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mn>6.4</mn></mrow></semantics></math></inline-formula> dB, respectively.https://www.mdpi.com/2079-9292/13/4/755self-testingalternative testingmixed-signal testingmanufacturing testproduction testbuilt-in self-test (BIST) |
| spellingShingle | Joonsung Park Jiwon Lee Jacob A. Abraham Byoungho Kim A Tunable Foreground Self-Calibration Scheme for Split Successive-Approximation Register Analog-to-Digital Converter Electronics self-testing alternative testing mixed-signal testing manufacturing test production test built-in self-test (BIST) |
| title | A Tunable Foreground Self-Calibration Scheme for Split Successive-Approximation Register Analog-to-Digital Converter |
| title_full | A Tunable Foreground Self-Calibration Scheme for Split Successive-Approximation Register Analog-to-Digital Converter |
| title_fullStr | A Tunable Foreground Self-Calibration Scheme for Split Successive-Approximation Register Analog-to-Digital Converter |
| title_full_unstemmed | A Tunable Foreground Self-Calibration Scheme for Split Successive-Approximation Register Analog-to-Digital Converter |
| title_short | A Tunable Foreground Self-Calibration Scheme for Split Successive-Approximation Register Analog-to-Digital Converter |
| title_sort | tunable foreground self calibration scheme for split successive approximation register analog to digital converter |
| topic | self-testing alternative testing mixed-signal testing manufacturing test production test built-in self-test (BIST) |
| url | https://www.mdpi.com/2079-9292/13/4/755 |
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