A New RTL Design Approach for a DCT/IDCT-Based Image Compression Architecture using the mCBE Algorithm
<p>In the literature, several approaches of designing a DCT/IDCT-based image compression system have been proposed. In this paper, we present a new RTL design approach with as main focus developing a DCT/IDCT-based image compression architecture using a self-created algorithm. ...
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| Format: | Article |
| Language: | English |
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ITB Journal Publisher
2013-09-01
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| Series: | Journal of ICT Research and Applications |
| Online Access: | http://journals.itb.ac.id/index.php/jictra/article/view/225 |
| _version_ | 1818313637383634944 |
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| author | Rachmad Vidya Wicaksana Putra Rella Mareta Nurfitri Anbarsanti Trio Adiono |
| author_facet | Rachmad Vidya Wicaksana Putra Rella Mareta Nurfitri Anbarsanti Trio Adiono |
| author_sort | Rachmad Vidya Wicaksana Putra |
| collection | DOAJ |
| description | <p>In the literature, several approaches of designing a DCT/IDCT-based image compression system have been proposed. In this paper, we present a new RTL design approach with as main focus developing a DCT/IDCT-based image compression architecture using a self-created algorithm. This algorithm can efficiently minimize the amount of shifter -adders to substitute multiplier s. We call this new algorithm the multiplication from Common Binary Expression (mCBE) Algorithm. Besides this algorithm, we propose alternative quantization numbers, which can be implemented simply as shifters in digital hardware. Mostly, these numbers can retain a good compressed-image quality compared to JPEG recommendations. These ideas lead to our design being small in circuit area, multiplierless, and low in complexity. The proposed 8-point 1D-DCT design has only six stages, while the 8-point 1D-IDCT design has only seven stages (one stage being defined as equal to the delay of one shifter or 2-input adder). By using the pipelining method, we can achieve a high-speed architecture with latency as a trade-off consideration. The design has been synthesized and can reach a speed of up to 1.41ns critical path delay (709.22MHz). </p> |
| first_indexed | 2024-12-13T08:36:55Z |
| format | Article |
| id | doaj.art-3cd653fc69fe481489cfe63678753377 |
| institution | Directory Open Access Journal |
| issn | 2337-5787 2338-5499 |
| language | English |
| last_indexed | 2024-12-13T08:36:55Z |
| publishDate | 2013-09-01 |
| publisher | ITB Journal Publisher |
| record_format | Article |
| series | Journal of ICT Research and Applications |
| spelling | doaj.art-3cd653fc69fe481489cfe636787533772022-12-21T23:53:37ZengITB Journal PublisherJournal of ICT Research and Applications2337-57872338-54992013-09-0162131150226A New RTL Design Approach for a DCT/IDCT-Based Image Compression Architecture using the mCBE AlgorithmRachmad Vidya Wicaksana Putra0Rella Mareta1Nurfitri Anbarsanti2Trio Adiono3IC Design Laboratory, Electrical Engineering, School of Electrical Engineering and Informatics, Institut Teknologi Bandung, Jalan Ganesha 10, Bandung 40132, IndonesiaIC Design Laboratory, Electrical Engineering, School of Electrical Engineering and Informatics, Institut Teknologi Bandung, Jalan Ganesha 10, Bandung 40132, IndonesiaIC Design Laboratory, Electrical Engineering, School of Electrical Engineering and Informatics, Institut Teknologi Bandung, Jalan Ganesha 10, Bandung 40132, IndonesiaIC Design Laboratory, Electrical Engineering, School of Electrical Engineering and Informatics, Institut Teknologi Bandung, Jalan Ganesha 10, Bandung 40132, Indonesia<p>In the literature, several approaches of designing a DCT/IDCT-based image compression system have been proposed. In this paper, we present a new RTL design approach with as main focus developing a DCT/IDCT-based image compression architecture using a self-created algorithm. This algorithm can efficiently minimize the amount of shifter -adders to substitute multiplier s. We call this new algorithm the multiplication from Common Binary Expression (mCBE) Algorithm. Besides this algorithm, we propose alternative quantization numbers, which can be implemented simply as shifters in digital hardware. Mostly, these numbers can retain a good compressed-image quality compared to JPEG recommendations. These ideas lead to our design being small in circuit area, multiplierless, and low in complexity. The proposed 8-point 1D-DCT design has only six stages, while the 8-point 1D-IDCT design has only seven stages (one stage being defined as equal to the delay of one shifter or 2-input adder). By using the pipelining method, we can achieve a high-speed architecture with latency as a trade-off consideration. The design has been synthesized and can reach a speed of up to 1.41ns critical path delay (709.22MHz). </p>http://journals.itb.ac.id/index.php/jictra/article/view/225 |
| spellingShingle | Rachmad Vidya Wicaksana Putra Rella Mareta Nurfitri Anbarsanti Trio Adiono A New RTL Design Approach for a DCT/IDCT-Based Image Compression Architecture using the mCBE Algorithm Journal of ICT Research and Applications |
| title | A New RTL Design Approach for a DCT/IDCT-Based Image Compression Architecture using the mCBE Algorithm |
| title_full | A New RTL Design Approach for a DCT/IDCT-Based Image Compression Architecture using the mCBE Algorithm |
| title_fullStr | A New RTL Design Approach for a DCT/IDCT-Based Image Compression Architecture using the mCBE Algorithm |
| title_full_unstemmed | A New RTL Design Approach for a DCT/IDCT-Based Image Compression Architecture using the mCBE Algorithm |
| title_short | A New RTL Design Approach for a DCT/IDCT-Based Image Compression Architecture using the mCBE Algorithm |
| title_sort | new rtl design approach for a dct idct based image compression architecture using the mcbe algorithm |
| url | http://journals.itb.ac.id/index.php/jictra/article/view/225 |
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