Sizing of SRAM Cell with Voltage Biasing Techniques for Reliability Enhancement of Memory and PUF Functions
Static Random Access Memory (SRAM) has recently been developed into a physical unclonable function (PUF) for generating chip-unique signatures for hardware cryptography. The most compelling issue in designing a good SRAM-based PUF (SPUF) is that while maximizing the mismatches between the transistor...
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| Format: | Article |
| Language: | English |
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MDPI AG
2016-08-01
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| Series: | Journal of Low Power Electronics and Applications |
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| Online Access: | http://www.mdpi.com/2079-9268/6/3/16 |
| _version_ | 1798025350636109824 |
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| author | Chip-Hong Chang Chao Qun Liu Le Zhang Zhi Hui Kong |
| author_facet | Chip-Hong Chang Chao Qun Liu Le Zhang Zhi Hui Kong |
| author_sort | Chip-Hong Chang |
| collection | DOAJ |
| description | Static Random Access Memory (SRAM) has recently been developed into a physical unclonable function (PUF) for generating chip-unique signatures for hardware cryptography. The most compelling issue in designing a good SRAM-based PUF (SPUF) is that while maximizing the mismatches between the transistors in the cross-coupled inverters improves the quality of the SPUF, this ironically also gives rise to increased memory read/write failures. For this reason, the memory cells of existing SPUFs cannot be reused as storage elements, which increases the overheads of cryptographic system where long signatures and high-density storage are both required. This paper presents a novel design methodology for dual-mode SRAM cell optimization. The design conflicts are resolved by using word-line voltage modulation, dynamic voltage scaling, negative bit-line and adaptive body bias techniques to compensate for reliability degradation due to transistor downsizing. The augmented circuit-level techniques expand the design space to achieve a good solution to fulfill several otherwise contradicting key design qualities for both modes of operation, as evinced by our statistical analysis and simulation results based on complementary metal–oxide–semiconductor (CMOS) 45 nm bulk Predictive Technology Model. |
| first_indexed | 2024-04-11T18:17:27Z |
| format | Article |
| id | doaj.art-3dd776efe77a4208b04bc15ec65e6ffb |
| institution | Directory Open Access Journal |
| issn | 2079-9268 |
| language | English |
| last_indexed | 2024-04-11T18:17:27Z |
| publishDate | 2016-08-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Journal of Low Power Electronics and Applications |
| spelling | doaj.art-3dd776efe77a4208b04bc15ec65e6ffb2022-12-22T04:09:51ZengMDPI AGJournal of Low Power Electronics and Applications2079-92682016-08-01631610.3390/jlpea6030016jlpea6030016Sizing of SRAM Cell with Voltage Biasing Techniques for Reliability Enhancement of Memory and PUF FunctionsChip-Hong Chang0Chao Qun Liu1Le Zhang2Zhi Hui Kong3School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, SingaporeSchool of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, SingaporeSchool of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, SingaporeSchool of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, SingaporeStatic Random Access Memory (SRAM) has recently been developed into a physical unclonable function (PUF) for generating chip-unique signatures for hardware cryptography. The most compelling issue in designing a good SRAM-based PUF (SPUF) is that while maximizing the mismatches between the transistors in the cross-coupled inverters improves the quality of the SPUF, this ironically also gives rise to increased memory read/write failures. For this reason, the memory cells of existing SPUFs cannot be reused as storage elements, which increases the overheads of cryptographic system where long signatures and high-density storage are both required. This paper presents a novel design methodology for dual-mode SRAM cell optimization. The design conflicts are resolved by using word-line voltage modulation, dynamic voltage scaling, negative bit-line and adaptive body bias techniques to compensate for reliability degradation due to transistor downsizing. The augmented circuit-level techniques expand the design space to achieve a good solution to fulfill several otherwise contradicting key design qualities for both modes of operation, as evinced by our statistical analysis and simulation results based on complementary metal–oxide–semiconductor (CMOS) 45 nm bulk Predictive Technology Model.http://www.mdpi.com/2079-9268/6/3/16physical unclonable function (PUF)hardware securityStatic Random Access Memory (SRAM)process variationmemory failures |
| spellingShingle | Chip-Hong Chang Chao Qun Liu Le Zhang Zhi Hui Kong Sizing of SRAM Cell with Voltage Biasing Techniques for Reliability Enhancement of Memory and PUF Functions Journal of Low Power Electronics and Applications physical unclonable function (PUF) hardware security Static Random Access Memory (SRAM) process variation memory failures |
| title | Sizing of SRAM Cell with Voltage Biasing Techniques for Reliability Enhancement of Memory and PUF Functions |
| title_full | Sizing of SRAM Cell with Voltage Biasing Techniques for Reliability Enhancement of Memory and PUF Functions |
| title_fullStr | Sizing of SRAM Cell with Voltage Biasing Techniques for Reliability Enhancement of Memory and PUF Functions |
| title_full_unstemmed | Sizing of SRAM Cell with Voltage Biasing Techniques for Reliability Enhancement of Memory and PUF Functions |
| title_short | Sizing of SRAM Cell with Voltage Biasing Techniques for Reliability Enhancement of Memory and PUF Functions |
| title_sort | sizing of sram cell with voltage biasing techniques for reliability enhancement of memory and puf functions |
| topic | physical unclonable function (PUF) hardware security Static Random Access Memory (SRAM) process variation memory failures |
| url | http://www.mdpi.com/2079-9268/6/3/16 |
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