A high level implementation and performance evaluation of level-I asynchronous cache on FPGA
To bridge the ever-increasing performance gap between the processor and the main memory in a cost-effective manner, novel cache designs and implementations are indispensable. Cache is responsible for a major part of energy consumption (approx. 50%) of processors. This paper presents a high level imp...
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| Format: | Article |
| Language: | English |
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Elsevier
2017-07-01
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| Series: | Journal of King Saud University: Computer and Information Sciences |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S1319157815001056 |
| _version_ | 1819240358130745344 |
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| author | Mansi Jhamb R.K. Sharma A.K. Gupta |
| author_facet | Mansi Jhamb R.K. Sharma A.K. Gupta |
| author_sort | Mansi Jhamb |
| collection | DOAJ |
| description | To bridge the ever-increasing performance gap between the processor and the main memory in a cost-effective manner, novel cache designs and implementations are indispensable. Cache is responsible for a major part of energy consumption (approx. 50%) of processors. This paper presents a high level implementation of a micropipelined asynchronous architecture of L1 cache. Due to the fact that each cache memory implementation is time consuming and error-prone process, a synthesizable and a configurable model proves out to be of immense help as it aids in generating a range of caches in a reproducible and quick fashion. The micropipelined cache, implemented using C-Elements acts as a distributed message-passing system. The RTL cache model implemented in this paper, comprising of data and instruction caches has a wide array of configurable parameters. In addition to timing robustness our implementation has high average cache throughput and low latency. The implemented architecture comprises of two direct-mapped, write-through caches for data and instruction. The architecture is implemented in a Field Programmable Gate Array (FPGA) chip using Very High Speed Integrated Circuit Hardware Description Language (VHSIC HDL) along with advanced synthesis and place-and-route tools. |
| first_indexed | 2024-12-23T14:06:44Z |
| format | Article |
| id | doaj.art-3ef48b9d265d416b8652c1eaef9e8cc0 |
| institution | Directory Open Access Journal |
| issn | 1319-1578 |
| language | English |
| last_indexed | 2024-12-23T14:06:44Z |
| publishDate | 2017-07-01 |
| publisher | Elsevier |
| record_format | Article |
| series | Journal of King Saud University: Computer and Information Sciences |
| spelling | doaj.art-3ef48b9d265d416b8652c1eaef9e8cc02022-12-21T17:44:09ZengElsevierJournal of King Saud University: Computer and Information Sciences1319-15782017-07-0129341042510.1016/j.jksuci.2015.06.003A high level implementation and performance evaluation of level-I asynchronous cache on FPGAMansi Jhamb0R.K. Sharma1A.K. Gupta2University School of Information and Communication Technology, Guru Gobind Singh Indraprastha University, Dwarka Sector 16C, New Delhi 110078, IndiaDepartment of Electronics and Communication Engineering, NIT Kurukshetra, IndiaDepartment of Electronics and Communication Engineering, NIT Kurukshetra, IndiaTo bridge the ever-increasing performance gap between the processor and the main memory in a cost-effective manner, novel cache designs and implementations are indispensable. Cache is responsible for a major part of energy consumption (approx. 50%) of processors. This paper presents a high level implementation of a micropipelined asynchronous architecture of L1 cache. Due to the fact that each cache memory implementation is time consuming and error-prone process, a synthesizable and a configurable model proves out to be of immense help as it aids in generating a range of caches in a reproducible and quick fashion. The micropipelined cache, implemented using C-Elements acts as a distributed message-passing system. The RTL cache model implemented in this paper, comprising of data and instruction caches has a wide array of configurable parameters. In addition to timing robustness our implementation has high average cache throughput and low latency. The implemented architecture comprises of two direct-mapped, write-through caches for data and instruction. The architecture is implemented in a Field Programmable Gate Array (FPGA) chip using Very High Speed Integrated Circuit Hardware Description Language (VHSIC HDL) along with advanced synthesis and place-and-route tools.http://www.sciencedirect.com/science/article/pii/S1319157815001056AsynchronousHandshakingCache |
| spellingShingle | Mansi Jhamb R.K. Sharma A.K. Gupta A high level implementation and performance evaluation of level-I asynchronous cache on FPGA Journal of King Saud University: Computer and Information Sciences Asynchronous Handshaking Cache |
| title | A high level implementation and performance evaluation of level-I asynchronous cache on FPGA |
| title_full | A high level implementation and performance evaluation of level-I asynchronous cache on FPGA |
| title_fullStr | A high level implementation and performance evaluation of level-I asynchronous cache on FPGA |
| title_full_unstemmed | A high level implementation and performance evaluation of level-I asynchronous cache on FPGA |
| title_short | A high level implementation and performance evaluation of level-I asynchronous cache on FPGA |
| title_sort | high level implementation and performance evaluation of level i asynchronous cache on fpga |
| topic | Asynchronous Handshaking Cache |
| url | http://www.sciencedirect.com/science/article/pii/S1319157815001056 |
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