Energy efficient IPC based dual compression for endurance enhancement of NVRAM as main memory in embedded devices
Abstract The Non‐Volatile Random Access Memory (NVRAM) is recently identified as the most upcoming main memory technology in Embedded and Internet of Things (IoT) systems due to its appealing qualities like zero static power consumption and great memory cell density. On the other hand, most NVRAMs h...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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Wiley
2023-07-01
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| Series: | IET Communications |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/cmu2.12625 |
| _version_ | 1797788860642492416 |
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| author | Shritharanyaa Jothimani Palanivelu Saravana Kumar Radhakrishnan Kumar Chandrasekaran Sourav Barua Hady H. Fayek |
| author_facet | Shritharanyaa Jothimani Palanivelu Saravana Kumar Radhakrishnan Kumar Chandrasekaran Sourav Barua Hady H. Fayek |
| author_sort | Shritharanyaa Jothimani Palanivelu |
| collection | DOAJ |
| description | Abstract The Non‐Volatile Random Access Memory (NVRAM) is recently identified as the most upcoming main memory technology in Embedded and Internet of Things (IoT) systems due to its appealing qualities like zero static power consumption and great memory cell density. On the other hand, most NVRAMs have low write endurance due to workload‐induced write variance, leading to more write activity at a few blocks of memory than the other blocks. Improving the endurance of NVRAM on embedded architectures is very critical due to the limited constraints of Embedded architectures. The main goal of this paper is to address the complexity of NVRAM designs, with a focus on embedded boards, and to create a prototype that enhances NVRAM endurance using a compression technique. Furthermore, this framework is not particular to a single NVRAM device. An Instruction Per Cycle based Dynamic Pattern Compression (IPC_DPC) model is developed to address NVRAM's high write latency and low endurance. The primary goal of the proposed IPC_DPC model is to minimize the energy utilization and latency of heavy workloads during the execution by pre‐determining the workload's instruction cycles. The IPC_DPC model initially divides the Low IPC and High IPC workloads and then compresses the workloads dynamically based on their IPC values compared to the threshold factor. As a result, IPC_DPC improves the compression ratio and reduces the write latencies associated with traditional compressors, significantly reducing the write activity and improving the lifetime of NVRAM. We implemented the proposed IPC_DPC model using GEM5 with a Raspberry Pi board and took IoMT, MiBench, and EEMBC benchmarks for evaluation. Compared to FPC, BDI, FNW, and DFPC models, the proposed IPC_DPC model is shown to be more efficient in terms of compression ratio (56.05%) and energy reduction (17%). |
| first_indexed | 2024-03-13T01:42:35Z |
| format | Article |
| id | doaj.art-3f36d81d0b93492db1e05fede3aa588c |
| institution | Directory Open Access Journal |
| issn | 1751-8628 1751-8636 |
| language | English |
| last_indexed | 2024-03-13T01:42:35Z |
| publishDate | 2023-07-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Communications |
| spelling | doaj.art-3f36d81d0b93492db1e05fede3aa588c2023-07-03T11:41:05ZengWileyIET Communications1751-86281751-86362023-07-0117111310132010.1049/cmu2.12625Energy efficient IPC based dual compression for endurance enhancement of NVRAM as main memory in embedded devicesShritharanyaa Jothimani Palanivelu0Saravana Kumar Radhakrishnan1Kumar Chandrasekaran2Sourav Barua3Hady H. Fayek4School of Electrical and Electronics Engineering VIT Bhopal Universiy Kothrikalan, Sehore Madhya Pradesh IndiaSchool of Electronics Engineering Vellore Institute of Technology Chennai Tamil Nadu IndiaM.Kumarasamy College of Engineering Karur IndiaGreen University of Bangladesh Dhaka BangladeshElectromechanics Engineering Heliopolis University Cairo EgyptAbstract The Non‐Volatile Random Access Memory (NVRAM) is recently identified as the most upcoming main memory technology in Embedded and Internet of Things (IoT) systems due to its appealing qualities like zero static power consumption and great memory cell density. On the other hand, most NVRAMs have low write endurance due to workload‐induced write variance, leading to more write activity at a few blocks of memory than the other blocks. Improving the endurance of NVRAM on embedded architectures is very critical due to the limited constraints of Embedded architectures. The main goal of this paper is to address the complexity of NVRAM designs, with a focus on embedded boards, and to create a prototype that enhances NVRAM endurance using a compression technique. Furthermore, this framework is not particular to a single NVRAM device. An Instruction Per Cycle based Dynamic Pattern Compression (IPC_DPC) model is developed to address NVRAM's high write latency and low endurance. The primary goal of the proposed IPC_DPC model is to minimize the energy utilization and latency of heavy workloads during the execution by pre‐determining the workload's instruction cycles. The IPC_DPC model initially divides the Low IPC and High IPC workloads and then compresses the workloads dynamically based on their IPC values compared to the threshold factor. As a result, IPC_DPC improves the compression ratio and reduces the write latencies associated with traditional compressors, significantly reducing the write activity and improving the lifetime of NVRAM. We implemented the proposed IPC_DPC model using GEM5 with a Raspberry Pi board and took IoMT, MiBench, and EEMBC benchmarks for evaluation. Compared to FPC, BDI, FNW, and DFPC models, the proposed IPC_DPC model is shown to be more efficient in terms of compression ratio (56.05%) and energy reduction (17%).https://doi.org/10.1049/cmu2.12625energy conservationpattern matching |
| spellingShingle | Shritharanyaa Jothimani Palanivelu Saravana Kumar Radhakrishnan Kumar Chandrasekaran Sourav Barua Hady H. Fayek Energy efficient IPC based dual compression for endurance enhancement of NVRAM as main memory in embedded devices IET Communications energy conservation pattern matching |
| title | Energy efficient IPC based dual compression for endurance enhancement of NVRAM as main memory in embedded devices |
| title_full | Energy efficient IPC based dual compression for endurance enhancement of NVRAM as main memory in embedded devices |
| title_fullStr | Energy efficient IPC based dual compression for endurance enhancement of NVRAM as main memory in embedded devices |
| title_full_unstemmed | Energy efficient IPC based dual compression for endurance enhancement of NVRAM as main memory in embedded devices |
| title_short | Energy efficient IPC based dual compression for endurance enhancement of NVRAM as main memory in embedded devices |
| title_sort | energy efficient ipc based dual compression for endurance enhancement of nvram as main memory in embedded devices |
| topic | energy conservation pattern matching |
| url | https://doi.org/10.1049/cmu2.12625 |
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