Flexible Convolver for Convolutional Neural Networks Deployment onto Hardware-Oriented Applications
This paper introduces a flexible convolver capable of adapting to the different convolution layer configurations of state-of-the-art Convolution Neural Networks (CNNs). The use of two proposed programmable components achieves this adaptability. A Programmable Line Buffer (PLB) based on Programmable...
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| Format: | Article |
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MDPI AG
2022-12-01
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| Series: | Applied Sciences |
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| Online Access: | https://www.mdpi.com/2076-3417/13/1/93 |
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| author | Moisés Arredondo-Velázquez Paulo Aaron Aguirre-Álvarez Alfredo Padilla-Medina Alejandro Espinosa-Calderon Juan Prado-Olivarez Javier Diaz-Carmona |
| author_facet | Moisés Arredondo-Velázquez Paulo Aaron Aguirre-Álvarez Alfredo Padilla-Medina Alejandro Espinosa-Calderon Juan Prado-Olivarez Javier Diaz-Carmona |
| author_sort | Moisés Arredondo-Velázquez |
| collection | DOAJ |
| description | This paper introduces a flexible convolver capable of adapting to the different convolution layer configurations of state-of-the-art Convolution Neural Networks (CNNs). The use of two proposed programmable components achieves this adaptability. A Programmable Line Buffer (PLB) based on Programmable Shift Registers (PSRs) allows the generation of the required convolution masks required for each processed CNN layer. The convolution layer computing is performed through a proposed programmable systolic array configured according to the target device resources. In order to maximize the device resource usage and to achieve a shortened processing time, the filter, data, and loop parallelisms are leveraged. These characteristics allow the described architecture to be scalable and implemented on any FPGA device targeting different applications. The convolver description was written in VHDL using the Intel Cyclone V 5CSXFC6D6F31C6N device as a reference. The experimental results show that the proposed computing method allows the processing of any CNN without requiring special adaptation for a specific application since the standard convolution algorithm is used. The proposed flexible convolver achieves competitive performance compared with those reported in related works. |
| first_indexed | 2024-03-11T10:08:43Z |
| format | Article |
| id | doaj.art-3f78a28bdc2944bc8c4f0d713f107aeb |
| institution | Directory Open Access Journal |
| issn | 2076-3417 |
| language | English |
| last_indexed | 2024-03-11T10:08:43Z |
| publishDate | 2022-12-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Applied Sciences |
| spelling | doaj.art-3f78a28bdc2944bc8c4f0d713f107aeb2023-11-16T14:50:36ZengMDPI AGApplied Sciences2076-34172022-12-011319310.3390/app13010093Flexible Convolver for Convolutional Neural Networks Deployment onto Hardware-Oriented ApplicationsMoisés Arredondo-Velázquez0Paulo Aaron Aguirre-Álvarez1Alfredo Padilla-Medina2Alejandro Espinosa-Calderon3Juan Prado-Olivarez4Javier Diaz-Carmona5Faculty of Physical and Mathematical Sciences, Benemérita Universidad Autónoma de Puebla, Puebla 72410, MexicoElectronics Engineering Department, Tecnológico Nacional de México en Celaya, Celaya 38010, MexicoElectronics Engineering Department, Tecnológico Nacional de México en Celaya, Celaya 38010, MexicoRegional Center for Optimization and Development of Equipment, Tecnológico Nacional de México, Celaya 38020, MexicoElectronics Engineering Department, Tecnológico Nacional de México en Celaya, Celaya 38010, MexicoElectronics Engineering Department, Tecnológico Nacional de México en Celaya, Celaya 38010, MexicoThis paper introduces a flexible convolver capable of adapting to the different convolution layer configurations of state-of-the-art Convolution Neural Networks (CNNs). The use of two proposed programmable components achieves this adaptability. A Programmable Line Buffer (PLB) based on Programmable Shift Registers (PSRs) allows the generation of the required convolution masks required for each processed CNN layer. The convolution layer computing is performed through a proposed programmable systolic array configured according to the target device resources. In order to maximize the device resource usage and to achieve a shortened processing time, the filter, data, and loop parallelisms are leveraged. These characteristics allow the described architecture to be scalable and implemented on any FPGA device targeting different applications. The convolver description was written in VHDL using the Intel Cyclone V 5CSXFC6D6F31C6N device as a reference. The experimental results show that the proposed computing method allows the processing of any CNN without requiring special adaptation for a specific application since the standard convolution algorithm is used. The proposed flexible convolver achieves competitive performance compared with those reported in related works.https://www.mdpi.com/2076-3417/13/1/93convolutional neural networks (CNN)hardware acceleratorssystolic arrayfield programmable gate arrays (FPGA)embedded systems |
| spellingShingle | Moisés Arredondo-Velázquez Paulo Aaron Aguirre-Álvarez Alfredo Padilla-Medina Alejandro Espinosa-Calderon Juan Prado-Olivarez Javier Diaz-Carmona Flexible Convolver for Convolutional Neural Networks Deployment onto Hardware-Oriented Applications Applied Sciences convolutional neural networks (CNN) hardware accelerators systolic array field programmable gate arrays (FPGA) embedded systems |
| title | Flexible Convolver for Convolutional Neural Networks Deployment onto Hardware-Oriented Applications |
| title_full | Flexible Convolver for Convolutional Neural Networks Deployment onto Hardware-Oriented Applications |
| title_fullStr | Flexible Convolver for Convolutional Neural Networks Deployment onto Hardware-Oriented Applications |
| title_full_unstemmed | Flexible Convolver for Convolutional Neural Networks Deployment onto Hardware-Oriented Applications |
| title_short | Flexible Convolver for Convolutional Neural Networks Deployment onto Hardware-Oriented Applications |
| title_sort | flexible convolver for convolutional neural networks deployment onto hardware oriented applications |
| topic | convolutional neural networks (CNN) hardware accelerators systolic array field programmable gate arrays (FPGA) embedded systems |
| url | https://www.mdpi.com/2076-3417/13/1/93 |
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