Design Framework for ReRAM-Based DNN Accelerators with Accuracy and Hardware Evaluation
To achieve faster design closure, there is a need to provide a design framework for the design of ReRAM-based DNN (deep neural network) accelerator at the early design stage. In this paper, we develop a high-level ReRAM-based DNN accelerator design framework. The proposed design framework has the fo...
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2022-07-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/11/13/2107 |
| _version_ | 1797480351173443584 |
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| author | Hsu-Yu Kao Shih-Hsu Huang Wei-Kai Cheng |
| author_facet | Hsu-Yu Kao Shih-Hsu Huang Wei-Kai Cheng |
| author_sort | Hsu-Yu Kao |
| collection | DOAJ |
| description | To achieve faster design closure, there is a need to provide a design framework for the design of ReRAM-based DNN (deep neural network) accelerator at the early design stage. In this paper, we develop a high-level ReRAM-based DNN accelerator design framework. The proposed design framework has the following three features. First, we consider ReRAM’s non-linear properties, including lognormal distribution, leakage current, IR drop, and sneak path. Thus, model accuracy and circuit performance can be accurately evaluated. Second, we use SystemC with TLM modeling method to build our virtual platform. To our knowledge, the proposed design framework is the first behavior-level ReRAM deep learning accelerator simulator that can simulate real hardware behavior. Third, the proposed design framework can evaluate not only model accuracy but also hardware cost. As a result, the proposed design framework can be used for behavior-level design space exploration. In the experiments, we have deployed different DNN models on the virtual platform. Circuit performance can be easily evaluated on the proposed design framework. Furthermore, experiment results also show that the noise effects are different in different ReRAM array architectures. Based on the proposed design framework, we can easily mitigate noise effects by tuning architecture parameters. |
| first_indexed | 2024-03-09T21:58:28Z |
| format | Article |
| id | doaj.art-40d41e68c7f843fc913d046f8c9cf708 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-09T21:58:28Z |
| publishDate | 2022-07-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-40d41e68c7f843fc913d046f8c9cf7082023-11-23T19:52:57ZengMDPI AGElectronics2079-92922022-07-011113210710.3390/electronics11132107Design Framework for ReRAM-Based DNN Accelerators with Accuracy and Hardware EvaluationHsu-Yu Kao0Shih-Hsu Huang1Wei-Kai Cheng2Department of Electronic Engineering, Chung Yuan Christian University, Taoyuan 320314, TaiwanDepartment of Electronic Engineering, Chung Yuan Christian University, Taoyuan 320314, TaiwanDepartment of Information and Computer Engineering, Chung Yuan Christian University, Taoyuan 320314, TaiwanTo achieve faster design closure, there is a need to provide a design framework for the design of ReRAM-based DNN (deep neural network) accelerator at the early design stage. In this paper, we develop a high-level ReRAM-based DNN accelerator design framework. The proposed design framework has the following three features. First, we consider ReRAM’s non-linear properties, including lognormal distribution, leakage current, IR drop, and sneak path. Thus, model accuracy and circuit performance can be accurately evaluated. Second, we use SystemC with TLM modeling method to build our virtual platform. To our knowledge, the proposed design framework is the first behavior-level ReRAM deep learning accelerator simulator that can simulate real hardware behavior. Third, the proposed design framework can evaluate not only model accuracy but also hardware cost. As a result, the proposed design framework can be used for behavior-level design space exploration. In the experiments, we have deployed different DNN models on the virtual platform. Circuit performance can be easily evaluated on the proposed design framework. Furthermore, experiment results also show that the noise effects are different in different ReRAM array architectures. Based on the proposed design framework, we can easily mitigate noise effects by tuning architecture parameters.https://www.mdpi.com/2079-9292/11/13/2107processing-in-memoriesdesign closureDNN acceleratorsnon-linear effectssimulator |
| spellingShingle | Hsu-Yu Kao Shih-Hsu Huang Wei-Kai Cheng Design Framework for ReRAM-Based DNN Accelerators with Accuracy and Hardware Evaluation Electronics processing-in-memories design closure DNN accelerators non-linear effects simulator |
| title | Design Framework for ReRAM-Based DNN Accelerators with Accuracy and Hardware Evaluation |
| title_full | Design Framework for ReRAM-Based DNN Accelerators with Accuracy and Hardware Evaluation |
| title_fullStr | Design Framework for ReRAM-Based DNN Accelerators with Accuracy and Hardware Evaluation |
| title_full_unstemmed | Design Framework for ReRAM-Based DNN Accelerators with Accuracy and Hardware Evaluation |
| title_short | Design Framework for ReRAM-Based DNN Accelerators with Accuracy and Hardware Evaluation |
| title_sort | design framework for reram based dnn accelerators with accuracy and hardware evaluation |
| topic | processing-in-memories design closure DNN accelerators non-linear effects simulator |
| url | https://www.mdpi.com/2079-9292/11/13/2107 |
| work_keys_str_mv | AT hsuyukao designframeworkforrerambaseddnnacceleratorswithaccuracyandhardwareevaluation AT shihhsuhuang designframeworkforrerambaseddnnacceleratorswithaccuracyandhardwareevaluation AT weikaicheng designframeworkforrerambaseddnnacceleratorswithaccuracyandhardwareevaluation |