Performance Metric Evaluation of Error-Tolerant Adders for 2D Image Blending
The hardware implementation of error-tolerant adders using the paradigm of approximate computing has considerably influenced the performance metrics, especially in applications that can compromise accuracy. The foundation for approximate processing is the inclusion of errors in the design to enhance...
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-08-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/11/15/2461 |
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| author | Tanya Mendez Subramanya G. Nayak Vasanth Kumar P. Vijay S. R. Vishnumurthy Kedlaya K. |
| author_facet | Tanya Mendez Subramanya G. Nayak Vasanth Kumar P. Vijay S. R. Vishnumurthy Kedlaya K. |
| author_sort | Tanya Mendez |
| collection | DOAJ |
| description | The hardware implementation of error-tolerant adders using the paradigm of approximate computing has considerably influenced the performance metrics, especially in applications that can compromise accuracy. The foundation for approximate processing is the inclusion of errors in the design to enhance the effectiveness and reduce the complexity. This work presents three base adders using the novel concept of error tolerance in digital VLSI design. The research is extended to construct nine variants of power and delay-efficient 16 and 32-bit error-tolerant carry select adders (CSLA). To attain optimization in power and delay, conventional CSLA is refined by substituting ripple carry adders (RCA) with the newly proposed selector unit to minimize the switching activity. The research work includes the power, area, and delay estimates of the design from synthesis using the gpdk-90 nm and gpdk-45 nm standard cell libraries. The proposed adders exhibit reduced delay, power dissipation, area, power delay product (PDP), energy delay product (EDP), and area delay product (ADP) compared to the existing approximate adders. The proposed adder is used in an image blending application. There is a significant improvement in the peak-signal-to-noise ratio (PSNR) in the blended image compared to the standard designs. |
| first_indexed | 2024-03-09T12:40:42Z |
| format | Article |
| id | doaj.art-40fc98b2f2224c67964ddc4d6838ca3b |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-09T12:40:42Z |
| publishDate | 2022-08-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-40fc98b2f2224c67964ddc4d6838ca3b2023-11-30T22:17:57ZengMDPI AGElectronics2079-92922022-08-011115246110.3390/electronics11152461Performance Metric Evaluation of Error-Tolerant Adders for 2D Image BlendingTanya Mendez0Subramanya G. Nayak1Vasanth Kumar P.2Vijay S. R.3Vishnumurthy Kedlaya K.4Department of Electronics & Communication Engineering, Manipal Institute of Technology, Manipal Academy of Higher Education, Manipal 576104, IndiaDepartment of Electronics & Communication Engineering, Manipal Institute of Technology, Manipal Academy of Higher Education, Manipal 576104, IndiaDepartment of Electronics & Communication Engineering, Manipal Institute of Technology, Manipal Academy of Higher Education, Manipal 576104, IndiaDepartment of Electronics & Communication Engineering, Manipal Institute of Technology, Manipal Academy of Higher Education, Manipal 576104, IndiaDepartment of Electronics & Communication Engineering, Manipal Institute of Technology, Manipal Academy of Higher Education, Manipal 576104, IndiaThe hardware implementation of error-tolerant adders using the paradigm of approximate computing has considerably influenced the performance metrics, especially in applications that can compromise accuracy. The foundation for approximate processing is the inclusion of errors in the design to enhance the effectiveness and reduce the complexity. This work presents three base adders using the novel concept of error tolerance in digital VLSI design. The research is extended to construct nine variants of power and delay-efficient 16 and 32-bit error-tolerant carry select adders (CSLA). To attain optimization in power and delay, conventional CSLA is refined by substituting ripple carry adders (RCA) with the newly proposed selector unit to minimize the switching activity. The research work includes the power, area, and delay estimates of the design from synthesis using the gpdk-90 nm and gpdk-45 nm standard cell libraries. The proposed adders exhibit reduced delay, power dissipation, area, power delay product (PDP), energy delay product (EDP), and area delay product (ADP) compared to the existing approximate adders. The proposed adder is used in an image blending application. There is a significant improvement in the peak-signal-to-noise ratio (PSNR) in the blended image compared to the standard designs.https://www.mdpi.com/2079-9292/11/15/2461carry select addererror-tolerant adderimage blendingpeak-signal-to-noise-ratioASIC |
| spellingShingle | Tanya Mendez Subramanya G. Nayak Vasanth Kumar P. Vijay S. R. Vishnumurthy Kedlaya K. Performance Metric Evaluation of Error-Tolerant Adders for 2D Image Blending Electronics carry select adder error-tolerant adder image blending peak-signal-to-noise-ratio ASIC |
| title | Performance Metric Evaluation of Error-Tolerant Adders for 2D Image Blending |
| title_full | Performance Metric Evaluation of Error-Tolerant Adders for 2D Image Blending |
| title_fullStr | Performance Metric Evaluation of Error-Tolerant Adders for 2D Image Blending |
| title_full_unstemmed | Performance Metric Evaluation of Error-Tolerant Adders for 2D Image Blending |
| title_short | Performance Metric Evaluation of Error-Tolerant Adders for 2D Image Blending |
| title_sort | performance metric evaluation of error tolerant adders for 2d image blending |
| topic | carry select adder error-tolerant adder image blending peak-signal-to-noise-ratio ASIC |
| url | https://www.mdpi.com/2079-9292/11/15/2461 |
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