CMOS-compatible ising machines built using bistable latches coupled through ferroelectric transistor arrays
Abstract Realizing compact and scalable Ising machines that are compatible with CMOS-process technology is crucial to the effectiveness and practicality of using such hardware platforms for accelerating computationally intractable problems. Besides the need for realizing compact Ising spins, the imp...
| Main Authors: | , , , , , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Nature Portfolio
2023-01-01
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| Series: | Scientific Reports |
| Online Access: | https://doi.org/10.1038/s41598-023-28217-8 |
| _version_ | 1811175869629071360 |
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| author | Antik Mallick Zijian Zhao Mohammad Khairul Bashar Shamiul Alam Md Mazharul Islam Yi Xiao Yixin Xu Ahmedullah Aziz Vijaykrishnan Narayanan Kai Ni Nikhil Shukla |
| author_facet | Antik Mallick Zijian Zhao Mohammad Khairul Bashar Shamiul Alam Md Mazharul Islam Yi Xiao Yixin Xu Ahmedullah Aziz Vijaykrishnan Narayanan Kai Ni Nikhil Shukla |
| author_sort | Antik Mallick |
| collection | DOAJ |
| description | Abstract Realizing compact and scalable Ising machines that are compatible with CMOS-process technology is crucial to the effectiveness and practicality of using such hardware platforms for accelerating computationally intractable problems. Besides the need for realizing compact Ising spins, the implementation of the coupling network, which describes the spin interaction, is also a potential bottleneck in the scalability of such platforms. Therefore, in this work, we propose an Ising machine platform that exploits the novel behavior of compact bi-stable CMOS-latches (cross-coupled inverters) as classical Ising spins interacting through highly scalable and CMOS-process compatible ferroelectric-HfO2-based Ferroelectric FETs (FeFETs) which act as coupling elements. We experimentally demonstrate the prototype building blocks of this system, and evaluate the scaling behavior of the system using simulations. Our work not only provides a pathway to realizing CMOS-compatible designs but also to overcoming their scaling challenges. |
| first_indexed | 2024-04-10T19:42:55Z |
| format | Article |
| id | doaj.art-418c0f5964624c908c8665c5c6ecfb87 |
| institution | Directory Open Access Journal |
| issn | 2045-2322 |
| language | English |
| last_indexed | 2024-04-10T19:42:55Z |
| publishDate | 2023-01-01 |
| publisher | Nature Portfolio |
| record_format | Article |
| series | Scientific Reports |
| spelling | doaj.art-418c0f5964624c908c8665c5c6ecfb872023-01-29T12:11:51ZengNature PortfolioScientific Reports2045-23222023-01-011311910.1038/s41598-023-28217-8CMOS-compatible ising machines built using bistable latches coupled through ferroelectric transistor arraysAntik Mallick0Zijian Zhao1Mohammad Khairul Bashar2Shamiul Alam3Md Mazharul Islam4Yi Xiao5Yixin Xu6Ahmedullah Aziz7Vijaykrishnan Narayanan8Kai Ni9Nikhil Shukla10Department of Electrical and Computer Engineering, University of VirginiaDepartment of Electrical and Microelectronic Engineering, Rochester Institute of TechnologyDepartment of Electrical and Computer Engineering, University of VirginiaDepartment of Electrical Engineering and Computer Science, University of TennesseeDepartment of Electrical Engineering and Computer Science, University of TennesseeDepartment of Computer Science and Engineering, Pennsylvania State UniversityDepartment of Computer Science and Engineering, Pennsylvania State UniversityDepartment of Electrical Engineering and Computer Science, University of TennesseeDepartment of Computer Science and Engineering, Pennsylvania State UniversityDepartment of Electrical and Microelectronic Engineering, Rochester Institute of TechnologyDepartment of Electrical and Computer Engineering, University of VirginiaAbstract Realizing compact and scalable Ising machines that are compatible with CMOS-process technology is crucial to the effectiveness and practicality of using such hardware platforms for accelerating computationally intractable problems. Besides the need for realizing compact Ising spins, the implementation of the coupling network, which describes the spin interaction, is also a potential bottleneck in the scalability of such platforms. Therefore, in this work, we propose an Ising machine platform that exploits the novel behavior of compact bi-stable CMOS-latches (cross-coupled inverters) as classical Ising spins interacting through highly scalable and CMOS-process compatible ferroelectric-HfO2-based Ferroelectric FETs (FeFETs) which act as coupling elements. We experimentally demonstrate the prototype building blocks of this system, and evaluate the scaling behavior of the system using simulations. Our work not only provides a pathway to realizing CMOS-compatible designs but also to overcoming their scaling challenges.https://doi.org/10.1038/s41598-023-28217-8 |
| spellingShingle | Antik Mallick Zijian Zhao Mohammad Khairul Bashar Shamiul Alam Md Mazharul Islam Yi Xiao Yixin Xu Ahmedullah Aziz Vijaykrishnan Narayanan Kai Ni Nikhil Shukla CMOS-compatible ising machines built using bistable latches coupled through ferroelectric transistor arrays Scientific Reports |
| title | CMOS-compatible ising machines built using bistable latches coupled through ferroelectric transistor arrays |
| title_full | CMOS-compatible ising machines built using bistable latches coupled through ferroelectric transistor arrays |
| title_fullStr | CMOS-compatible ising machines built using bistable latches coupled through ferroelectric transistor arrays |
| title_full_unstemmed | CMOS-compatible ising machines built using bistable latches coupled through ferroelectric transistor arrays |
| title_short | CMOS-compatible ising machines built using bistable latches coupled through ferroelectric transistor arrays |
| title_sort | cmos compatible ising machines built using bistable latches coupled through ferroelectric transistor arrays |
| url | https://doi.org/10.1038/s41598-023-28217-8 |
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