Parasitic Coupling in 3D Sequential Integration: The Example of a Two-Layer 3D Pixel
In this paper, we present a thorough analysis of parasitic coupling effects between different electrodes for a 3D Sequential Integration circuit example comprising stacked devices. More specifically, this study is performed for a Back-Side Illuminated, 4T–APS, 3D Sequential Integration pixel with bo...
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-02-01
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| Series: | Technologies |
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| Online Access: | https://www.mdpi.com/2227-7080/10/2/38 |
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| author | Petros Sideris Arnaud Peizerat Perrine Batude Gilles Sicard Christoforos Theodorou |
| author_facet | Petros Sideris Arnaud Peizerat Perrine Batude Gilles Sicard Christoforos Theodorou |
| author_sort | Petros Sideris |
| collection | DOAJ |
| description | In this paper, we present a thorough analysis of parasitic coupling effects between different electrodes for a 3D Sequential Integration circuit example comprising stacked devices. More specifically, this study is performed for a Back-Side Illuminated, 4T–APS, 3D Sequential Integration pixel with both its photodiode and Transfer Gate at the bottom tier and the other parts of the circuit on the top tier. The effects of voltage bias and 3D inter-tier contacts are studied by using TCAD simulations. Coupling-induced electrical parameter variations are compared against variations due to temperature change, revealing that these two effects can cause similar levels of readout error for the top-tier readout circuit. On the bright side, we also demonstrate that in the case of a rolling shutter pixel readout, the coupling effect becomes nearly negligible. Therefore, we estimate that the presence of an inter-tier ground plane, normally used for electrical isolation, is not strictly mandatory for Monolithic 3D pixels. |
| first_indexed | 2024-03-09T04:10:31Z |
| format | Article |
| id | doaj.art-41ebbdc9c9b745698489d7fe1b25f5c1 |
| institution | Directory Open Access Journal |
| issn | 2227-7080 |
| language | English |
| last_indexed | 2024-03-09T04:10:31Z |
| publishDate | 2022-02-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Technologies |
| spelling | doaj.art-41ebbdc9c9b745698489d7fe1b25f5c12023-12-03T14:00:59ZengMDPI AGTechnologies2227-70802022-02-011023810.3390/technologies10020038Parasitic Coupling in 3D Sequential Integration: The Example of a Two-Layer 3D PixelPetros Sideris0Arnaud Peizerat1Perrine Batude2Gilles Sicard3Christoforos Theodorou4University Grenoble Alpes, Univ. Savoie Mont Blanc, Centre National de la Recherche Scientifique (CNRS), Grenoble INstitut Polytechnique (Grenoble INP), Institut de Microélectronique Electromagnétisme Photonique-LAboratoire d′Hyperfréquences et de Caractérisation (IMEP—LAHC), 38000 Grenoble, FranceCommissariat à l’Energie Atomique et aux Energies Alternatives—Laboratoire d′Electronique des Technologies de l′Information (CEA—LETI), University Grenoble Alpes, 38054 Grenoble, FranceCommissariat à l’Energie Atomique et aux Energies Alternatives—Laboratoire d′Electronique des Technologies de l′Information (CEA—LETI), University Grenoble Alpes, 38054 Grenoble, FranceCommissariat à l’Energie Atomique et aux Energies Alternatives—Laboratoire d′Electronique des Technologies de l′Information (CEA—LETI), University Grenoble Alpes, 38054 Grenoble, FranceUniversity Grenoble Alpes, Univ. Savoie Mont Blanc, Centre National de la Recherche Scientifique (CNRS), Grenoble INstitut Polytechnique (Grenoble INP), Institut de Microélectronique Electromagnétisme Photonique-LAboratoire d′Hyperfréquences et de Caractérisation (IMEP—LAHC), 38000 Grenoble, FranceIn this paper, we present a thorough analysis of parasitic coupling effects between different electrodes for a 3D Sequential Integration circuit example comprising stacked devices. More specifically, this study is performed for a Back-Side Illuminated, 4T–APS, 3D Sequential Integration pixel with both its photodiode and Transfer Gate at the bottom tier and the other parts of the circuit on the top tier. The effects of voltage bias and 3D inter-tier contacts are studied by using TCAD simulations. Coupling-induced electrical parameter variations are compared against variations due to temperature change, revealing that these two effects can cause similar levels of readout error for the top-tier readout circuit. On the bright side, we also demonstrate that in the case of a rolling shutter pixel readout, the coupling effect becomes nearly negligible. Therefore, we estimate that the presence of an inter-tier ground plane, normally used for electrical isolation, is not strictly mandatory for Monolithic 3D pixels.https://www.mdpi.com/2227-7080/10/2/38image sensors3D pixels3D sequential integration3DSImonolithic 3DM3D |
| spellingShingle | Petros Sideris Arnaud Peizerat Perrine Batude Gilles Sicard Christoforos Theodorou Parasitic Coupling in 3D Sequential Integration: The Example of a Two-Layer 3D Pixel Technologies image sensors 3D pixels 3D sequential integration 3DSI monolithic 3D M3D |
| title | Parasitic Coupling in 3D Sequential Integration: The Example of a Two-Layer 3D Pixel |
| title_full | Parasitic Coupling in 3D Sequential Integration: The Example of a Two-Layer 3D Pixel |
| title_fullStr | Parasitic Coupling in 3D Sequential Integration: The Example of a Two-Layer 3D Pixel |
| title_full_unstemmed | Parasitic Coupling in 3D Sequential Integration: The Example of a Two-Layer 3D Pixel |
| title_short | Parasitic Coupling in 3D Sequential Integration: The Example of a Two-Layer 3D Pixel |
| title_sort | parasitic coupling in 3d sequential integration the example of a two layer 3d pixel |
| topic | image sensors 3D pixels 3D sequential integration 3DSI monolithic 3D M3D |
| url | https://www.mdpi.com/2227-7080/10/2/38 |
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