Templatized Fused Vector Floating-Point Dot Product for High-Level Synthesis
Machine-learning accelerators rely on floating-point matrix and vector multiplication kernels. To reduce their cost, customized many-term fused architectures are preferred, which improve the latency, power, and area of the designs. In this work, we design a parameterized fused many-term floating-poi...
Main Authors: | Dionysios Filippas, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos |
---|---|
Format: | Article |
Language: | English |
Published: |
MDPI AG
2022-10-01
|
Series: | Journal of Low Power Electronics and Applications |
Subjects: | |
Online Access: | https://www.mdpi.com/2079-9268/12/4/56 |
Similar Items
-
IEEE single precision floating point divider /
by: 224950 Lim, Kae Yih
Published: (2005) -
Floating-point unit multiplier /
by: 427299 Yeoh, Kevin Wee Lee
Published: (2003) -
Binary floating point arithmetic for microprocessor systems
by: 8096 British Standards Institution -
Efficient Floating Point Arithmetic for Quantum Computers
by: Raphael Seidel, et al.
Published: (2022-01-01) -
A IEEE floating-point multiplier /
by: 237377 Ong, Lay Cheng
Published: (2005)