FPGAN: An FPGA Accelerator for Graph Attention Networks With Software and Hardware Co-Optimization
The Graph Attention Networks (GATs) exhibit outstanding performance in multiple authoritative node classification benchmark tests (including transductive and inductive). The purpose of this research is to implement an FPGA-based accelerator called FPGAN for graph attention networks that achieves sig...
Main Authors: | Weian Yan, Weiqin Tong, Xiaoli Zhi |
---|---|
Format: | Article |
Language: | English |
Published: |
IEEE
2020-01-01
|
Series: | IEEE Access |
Subjects: | |
Online Access: | https://ieeexplore.ieee.org/document/9195849/ |
Similar Items
-
Model Parallelism Optimization for CNN FPGA Accelerator
by: Jinnan Wang, et al.
Published: (2023-02-01) -
Preconditioned Conjugate Gradient Acceleration on FPGA-Based Platforms
by: Pavlos Malakonakis, et al.
Published: (2022-09-01) -
FPGA based automated hardware verification system /
by: Kee, Woei Chee , author, et al.
Published: (2009) -
FPGA-Based Hardware Accelerator Design and Implementation of Oil Palm Detection
by: YUAN Ming, CHAI Zhilei, GAN Lin
Published: (2021-02-01) -
FPGA implementation of a lossless universal data compression hardware /
by: Mohamed Khalil Mohd. Hani 608642, et al.
Published: (2002)