FPGA architecture based on OpenCL for studying the acoustic backscattering by an immersed tube
At a time when the semiconductor industry is facing major difficulties in maintaining sluggish growth, new high-level synthesis tools are repositioning FPGAs as a leading technology for hardware-based algorithm acceleration, in the face of CPUs based clusters. As they stand, however, these tools do...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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Elsevier
2024-02-01
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| Series: | Heliyon |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2405844024020188 |
| _version_ | 1797267729895391232 |
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| author | Mhamed Hadji Abdelkader Elhanaoui Rachid Skouri Said Agounad |
| author_facet | Mhamed Hadji Abdelkader Elhanaoui Rachid Skouri Said Agounad |
| author_sort | Mhamed Hadji |
| collection | DOAJ |
| description | At a time when the semiconductor industry is facing major difficulties in maintaining sluggish growth, new high-level synthesis tools are repositioning FPGAs as a leading technology for hardware-based algorithm acceleration, in the face of CPUs based clusters. As they stand, however, these tools do not guarantee that a software engineer can use these technologies to their full potential without expertise in the underlying hardware. This particularity can be an obstacle to their democratization. When it comes to acoustic scattering (AS) and its various applications, there is a growing need for autonomous and integrated systems that can operate in real time with high accuracy. This is why we propose our methodology for accelerating algorithms on FPGAs. After presenting a high-level architecture model of this target, we detail various possible optimizations in OpenCL, to finally define a relevant exploration strategy for algorithm acceleration on FPGAs. Applied to various case studies, to characterize and identify an immersed metal tube in the frequency range between 0 and 46.8 kHz. We evaluate our methodology according to three main performance criteria: execution time, resource utilization and energy efficiency. The experimental results show that the proposed methodology is efficient and effective. Indeed, the computation times using the DE1 Soc FPGA and a modern CPU are about 3.5s and 74s respectively. In addition, the absolute error did not exceed 10−5. |
| first_indexed | 2024-03-07T22:54:09Z |
| format | Article |
| id | doaj.art-458390ee27494b7188f3bc40ae915036 |
| institution | Directory Open Access Journal |
| issn | 2405-8440 |
| language | English |
| last_indexed | 2024-04-25T01:21:13Z |
| publishDate | 2024-02-01 |
| publisher | Elsevier |
| record_format | Article |
| series | Heliyon |
| spelling | doaj.art-458390ee27494b7188f3bc40ae9150362024-03-09T09:26:47ZengElsevierHeliyon2405-84402024-02-01104e25987FPGA architecture based on OpenCL for studying the acoustic backscattering by an immersed tubeMhamed Hadji0Abdelkader Elhanaoui1Rachid Skouri2Said Agounad3REPTI, Faculty of Sciences and Technology, BP 509, Boutalamine, Errachida, Moulay Ismail University of Meknès, Morocco; Corresponding author.REPTI, Faculty of Sciences and Technology, BP 509, Boutalamine, Errachida, Moulay Ismail University of Meknès, Morocco; LMTI, Faculty of Sciences, Ibn Zohr University Agadir, MoroccoAMES, High School of Technology, Km 5, Road of Agouray N6, Moulay Ismail University of Meknès, MoroccoLMTI, Faculty of Sciences, Ibn Zohr University Agadir, MoroccoAt a time when the semiconductor industry is facing major difficulties in maintaining sluggish growth, new high-level synthesis tools are repositioning FPGAs as a leading technology for hardware-based algorithm acceleration, in the face of CPUs based clusters. As they stand, however, these tools do not guarantee that a software engineer can use these technologies to their full potential without expertise in the underlying hardware. This particularity can be an obstacle to their democratization. When it comes to acoustic scattering (AS) and its various applications, there is a growing need for autonomous and integrated systems that can operate in real time with high accuracy. This is why we propose our methodology for accelerating algorithms on FPGAs. After presenting a high-level architecture model of this target, we detail various possible optimizations in OpenCL, to finally define a relevant exploration strategy for algorithm acceleration on FPGAs. Applied to various case studies, to characterize and identify an immersed metal tube in the frequency range between 0 and 46.8 kHz. We evaluate our methodology according to three main performance criteria: execution time, resource utilization and energy efficiency. The experimental results show that the proposed methodology is efficient and effective. Indeed, the computation times using the DE1 Soc FPGA and a modern CPU are about 3.5s and 74s respectively. In addition, the absolute error did not exceed 10−5.http://www.sciencedirect.com/science/article/pii/S2405844024020188Acoustic scattering (AS)Signal processing systemOpenCL programmingEmbedded architectures |
| spellingShingle | Mhamed Hadji Abdelkader Elhanaoui Rachid Skouri Said Agounad FPGA architecture based on OpenCL for studying the acoustic backscattering by an immersed tube Heliyon Acoustic scattering (AS) Signal processing system OpenCL programming Embedded architectures |
| title | FPGA architecture based on OpenCL for studying the acoustic backscattering by an immersed tube |
| title_full | FPGA architecture based on OpenCL for studying the acoustic backscattering by an immersed tube |
| title_fullStr | FPGA architecture based on OpenCL for studying the acoustic backscattering by an immersed tube |
| title_full_unstemmed | FPGA architecture based on OpenCL for studying the acoustic backscattering by an immersed tube |
| title_short | FPGA architecture based on OpenCL for studying the acoustic backscattering by an immersed tube |
| title_sort | fpga architecture based on opencl for studying the acoustic backscattering by an immersed tube |
| topic | Acoustic scattering (AS) Signal processing system OpenCL programming Embedded architectures |
| url | http://www.sciencedirect.com/science/article/pii/S2405844024020188 |
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