Understanding Timing Error Characteristics from Overclocked Systolic Multiply–Accumulate Arrays in FPGAs

Understanding Timing Error Characteristics from Overclocked Systolic Multiply–Accumulate Arrays in FPGAs

Artificial Intelligence (AI) hardware accelerators have seen tremendous developments in recent years due to the rapid growth of AI in multiple fields. Many such accelerators comprise a Systolic Multiply–Accumulate Array (SMA) as its computational brain. In this paper, we investigate the faulty outpu...

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Bibliographic Details
Main Authors: Andrew Chamberlin, Andrew Gerber, Mason Palmer, Tim Goodale, Noel Daniel Gundi, Koushik Chakraborty, Sanghamitra Roy
Format: Article
Language:English
Published: MDPI AG 2024-01-01
Series:Journal of Low Power Electronics and Applications
Subjects:
AI hardware accelerator
timing errors
FPGA
tensor flow
Online Access:https://www.mdpi.com/2079-9268/14/1/4

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