Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits

This paper introduces a plug-and-play on-chip asynchronous communication network aimed at the dynamic reconfiguration of a low-power adaptive circuit such as an internet of things (IoT) system. By using a separate communication network, we can address both digital and analog blocks at a lower config...

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Main Authors: Soundous Chairat, Edith Beigne, Ivan Miro-Panades, Marc Belleville
Format: Article
Language:English
Published: MDPI AG 2017-05-01
Series:Journal of Low Power Electronics and Applications
Subjects:
Online Access:http://www.mdpi.com/2079-9268/7/2/11
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author Soundous Chairat
Edith Beigne
Ivan Miro-Panades
Marc Belleville
author_facet Soundous Chairat
Edith Beigne
Ivan Miro-Panades
Marc Belleville
author_sort Soundous Chairat
collection DOAJ
description This paper introduces a plug-and-play on-chip asynchronous communication network aimed at the dynamic reconfiguration of a low-power adaptive circuit such as an internet of things (IoT) system. By using a separate communication network, we can address both digital and analog blocks at a lower configuration cost, increasing the overall system power efficiency. As reconfiguration only occurs according to specific events and has to be automatically in stand-by most of the time, our design is fully asynchronous using handshake protocols. The paper presents the circuit’s architecture, performance results, and an example of the reconfiguration of frequency locked loops (FLL) to validate our work. We obtain an overall energy per bit of 0.07 pJ/bit for one stage, in a 28 nm Fully Depleted Silicon On Insulator (FDSOI) technology at 0.6 V and a 1.1 ns/bit latency per stage.
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spelling doaj.art-45fba3c517d844df92b0ba1ac58047df2022-12-22T03:19:15ZengMDPI AGJournal of Low Power Electronics and Applications2079-92682017-05-01721110.3390/jlpea7020011jlpea7020011Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive CircuitsSoundous Chairat0Edith Beigne1Ivan Miro-Panades2Marc Belleville3University Grenoble Alpes, CEA, Leti, F-38000 Grenoble, FranceUniversity Grenoble Alpes, CEA, Leti, F-38000 Grenoble, FranceUniversity Grenoble Alpes, CEA, Leti, F-38000 Grenoble, FranceUniversity Grenoble Alpes, CEA, Leti, F-38000 Grenoble, FranceThis paper introduces a plug-and-play on-chip asynchronous communication network aimed at the dynamic reconfiguration of a low-power adaptive circuit such as an internet of things (IoT) system. By using a separate communication network, we can address both digital and analog blocks at a lower configuration cost, increasing the overall system power efficiency. As reconfiguration only occurs according to specific events and has to be automatically in stand-by most of the time, our design is fully asynchronous using handshake protocols. The paper presents the circuit’s architecture, performance results, and an example of the reconfiguration of frequency locked loops (FLL) to validate our work. We obtain an overall energy per bit of 0.07 pJ/bit for one stage, in a 28 nm Fully Depleted Silicon On Insulator (FDSOI) technology at 0.6 V and a 1.1 ns/bit latency per stage.http://www.mdpi.com/2079-9268/7/2/11on-chip communication networkadaptive blocksasynchronous design
spellingShingle Soundous Chairat
Edith Beigne
Ivan Miro-Panades
Marc Belleville
Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits
Journal of Low Power Electronics and Applications
on-chip communication network
adaptive blocks
asynchronous design
title Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits
title_full Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits
title_fullStr Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits
title_full_unstemmed Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits
title_short Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits
title_sort ultra low energy fdsoi asynchronous reconfiguration network for adaptive circuits
topic on-chip communication network
adaptive blocks
asynchronous design
url http://www.mdpi.com/2079-9268/7/2/11
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AT edithbeigne ultralowenergyfdsoiasynchronousreconfigurationnetworkforadaptivecircuits
AT ivanmiropanades ultralowenergyfdsoiasynchronousreconfigurationnetworkforadaptivecircuits
AT marcbelleville ultralowenergyfdsoiasynchronousreconfigurationnetworkforadaptivecircuits