FPGA-Based Bee Counter System
The bee counter described in this paper is a device that is installed at the entrance of the hive and forces the bees to pass through one of its twenty passageways. Each passageway has an LED at the top, which emits infrared light, and at the bottom a double photodiode integrated in the same package...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/10443621/ |
| _version_ | 1797272680319156224 |
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| author | Francisco J. Quiles-Latorre Manuel Ortiz-Lopez Francisco J. Rodriguez-Lozano M. Brox Jose M. Flores |
| author_facet | Francisco J. Quiles-Latorre Manuel Ortiz-Lopez Francisco J. Rodriguez-Lozano M. Brox Jose M. Flores |
| author_sort | Francisco J. Quiles-Latorre |
| collection | DOAJ |
| description | The bee counter described in this paper is a device that is installed at the entrance of the hive and forces the bees to pass through one of its twenty passageways. Each passageway has an LED at the top, which emits infrared light, and at the bottom a double photodiode integrated in the same package, which generates electrical pulses when the bee passes through the passageway and cuts the light beam. The pulses are monitored by an FPGA that counts the number of bees entering and leaving the passageway, each of which has its own control unit, implemented in the FPGA, achieving a correct and independent interpretation of the temporal relationship between the two pulses. Furthermore, the sampling frequency of the pulses and the small distance between the photodiodes, because they are in the same encapsulation, make it possible to detect the input or output of bees moving very close to each other, with a minimum distance of approximately 1 mm. In addition, the fact that each passageway has its own control unit makes it possible to detect anomalous conditions due to a failure in the LED or photodiodes, or anomalies caused even by the bees as the propolis. For these cases, a timer associated to each passageway in the FPGA has been included, which starts a timer when one of the two photodiodes does not detect a light beam. The counter has two working modes: connected to a host or in stand-alone mode, in which it periodically sends the bee count. The counter has an UART of ABR (Automatic Baud Rate) type where it receives the AT commands sent by the host to request the input and output counts and the status of the passageways. The answer data corresponding to the command are also sent to the host through the UART. The FPGA description has been performed in VHDL and customizable so that it can be implemented for any number of passageways on any FPGA. The system was evaluated in three hives from August 2nd to September 23rd, 2020, during the end of the summer season and the previous results are also shown in this work. |
| first_indexed | 2024-03-07T14:32:49Z |
| format | Article |
| id | doaj.art-464ad7040aa84229ab9cd02da3b021f2 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-03-07T14:32:49Z |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-464ad7040aa84229ab9cd02da3b021f22024-03-06T00:00:46ZengIEEEIEEE Access2169-35362024-01-0112303623038110.1109/ACCESS.2024.336904510443621FPGA-Based Bee Counter SystemFrancisco J. Quiles-Latorre0https://orcid.org/0000-0002-2180-2497Manuel Ortiz-Lopez1https://orcid.org/0000-0001-8312-1729Francisco J. Rodriguez-Lozano2https://orcid.org/0000-0003-3560-1407M. Brox3https://orcid.org/0000-0002-4002-3253Jose M. Flores4https://orcid.org/0000-0002-2238-4610Department of Electronic and Computer Engineering, Universidad de Córdoba, Córdoba, SpainDepartment of Electronic and Computer Engineering, Universidad de Córdoba, Córdoba, SpainDepartment of Electronic and Computer Engineering, Universidad de Córdoba, Córdoba, SpainDepartment of Electronic and Computer Engineering, Universidad de Córdoba, Córdoba, SpainDepartment of Zoology, Universidad de Córdoba, Campus de Rabanales, Córdoba, SpainThe bee counter described in this paper is a device that is installed at the entrance of the hive and forces the bees to pass through one of its twenty passageways. Each passageway has an LED at the top, which emits infrared light, and at the bottom a double photodiode integrated in the same package, which generates electrical pulses when the bee passes through the passageway and cuts the light beam. The pulses are monitored by an FPGA that counts the number of bees entering and leaving the passageway, each of which has its own control unit, implemented in the FPGA, achieving a correct and independent interpretation of the temporal relationship between the two pulses. Furthermore, the sampling frequency of the pulses and the small distance between the photodiodes, because they are in the same encapsulation, make it possible to detect the input or output of bees moving very close to each other, with a minimum distance of approximately 1 mm. In addition, the fact that each passageway has its own control unit makes it possible to detect anomalous conditions due to a failure in the LED or photodiodes, or anomalies caused even by the bees as the propolis. For these cases, a timer associated to each passageway in the FPGA has been included, which starts a timer when one of the two photodiodes does not detect a light beam. The counter has two working modes: connected to a host or in stand-alone mode, in which it periodically sends the bee count. The counter has an UART of ABR (Automatic Baud Rate) type where it receives the AT commands sent by the host to request the input and output counts and the status of the passageways. The answer data corresponding to the command are also sent to the host through the UART. The FPGA description has been performed in VHDL and customizable so that it can be implemented for any number of passageways on any FPGA. The system was evaluated in three hives from August 2nd to September 23rd, 2020, during the end of the summer season and the previous results are also shown in this work.https://ieeexplore.ieee.org/document/10443621/Beekeepingbee monitoringfield programmable gate arraysinstrumentation and measurement |
| spellingShingle | Francisco J. Quiles-Latorre Manuel Ortiz-Lopez Francisco J. Rodriguez-Lozano M. Brox Jose M. Flores FPGA-Based Bee Counter System IEEE Access Beekeeping bee monitoring field programmable gate arrays instrumentation and measurement |
| title | FPGA-Based Bee Counter System |
| title_full | FPGA-Based Bee Counter System |
| title_fullStr | FPGA-Based Bee Counter System |
| title_full_unstemmed | FPGA-Based Bee Counter System |
| title_short | FPGA-Based Bee Counter System |
| title_sort | fpga based bee counter system |
| topic | Beekeeping bee monitoring field programmable gate arrays instrumentation and measurement |
| url | https://ieeexplore.ieee.org/document/10443621/ |
| work_keys_str_mv | AT franciscojquileslatorre fpgabasedbeecountersystem AT manuelortizlopez fpgabasedbeecountersystem AT franciscojrodriguezlozano fpgabasedbeecountersystem AT mbrox fpgabasedbeecountersystem AT josemflores fpgabasedbeecountersystem |