Feasibility Prediction for Rapid IC Design Space Exploration

The DARPA POSH program echoes with the research community and identifies that engineering productivity has fallen behind Moore’s law, resulting in the prohibitive increase in IC design cost at leading technology nodes. The primary reason is that it requires many computing resources, expensive tools,...

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Main Author: Riadul Islam
Format: Article
Language:English
Published: MDPI AG 2022-04-01
Series:Electronics
Subjects:
Online Access:https://www.mdpi.com/2079-9292/11/7/1161
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author Riadul Islam
author_facet Riadul Islam
author_sort Riadul Islam
collection DOAJ
description The DARPA POSH program echoes with the research community and identifies that engineering productivity has fallen behind Moore’s law, resulting in the prohibitive increase in IC design cost at leading technology nodes. The primary reason is that it requires many computing resources, expensive tools, and even many days to complete a design implementation. However, at the end of this process, some designs could not meet the design constraints and become unroutable, creating a vicious circuit design cycle. As a result, designers have to re-run the whole process after design modification. This research applied a machine learning approach to automatically identify design constraints and design rule checking (DRC) violation issues and help the designer identify design constraints with optimal DRCs before the long detailed routing process through iterative greedy search. The proposed algorithm achieved up to 99.99% design constraint prediction accuracy and reduced 98.4% DRC violations with only a 6.9% area penalty.
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spelling doaj.art-467bfa11eff7469c8a94e08fc1aa89452023-11-30T23:08:17ZengMDPI AGElectronics2079-92922022-04-01117116110.3390/electronics11071161Feasibility Prediction for Rapid IC Design Space ExplorationRiadul Islam0Department of Computer Science and Electrical Engineering, University of Maryland Baltimore County, Baltimore, MD 21250, USAThe DARPA POSH program echoes with the research community and identifies that engineering productivity has fallen behind Moore’s law, resulting in the prohibitive increase in IC design cost at leading technology nodes. The primary reason is that it requires many computing resources, expensive tools, and even many days to complete a design implementation. However, at the end of this process, some designs could not meet the design constraints and become unroutable, creating a vicious circuit design cycle. As a result, designers have to re-run the whole process after design modification. This research applied a machine learning approach to automatically identify design constraints and design rule checking (DRC) violation issues and help the designer identify design constraints with optimal DRCs before the long detailed routing process through iterative greedy search. The proposed algorithm achieved up to 99.99% design constraint prediction accuracy and reduced 98.4% DRC violations with only a 6.9% area penalty.https://www.mdpi.com/2079-9292/11/7/1161design rule checkelectronic design automation (EDA)decision treeIC designdesign constraints
spellingShingle Riadul Islam
Feasibility Prediction for Rapid IC Design Space Exploration
Electronics
design rule check
electronic design automation (EDA)
decision tree
IC design
design constraints
title Feasibility Prediction for Rapid IC Design Space Exploration
title_full Feasibility Prediction for Rapid IC Design Space Exploration
title_fullStr Feasibility Prediction for Rapid IC Design Space Exploration
title_full_unstemmed Feasibility Prediction for Rapid IC Design Space Exploration
title_short Feasibility Prediction for Rapid IC Design Space Exploration
title_sort feasibility prediction for rapid ic design space exploration
topic design rule check
electronic design automation (EDA)
decision tree
IC design
design constraints
url https://www.mdpi.com/2079-9292/11/7/1161
work_keys_str_mv AT riadulislam feasibilitypredictionforrapidicdesignspaceexploration