Experimental Verification of Triple Lobes Generation in Fractional Memristive Circuits
Recently, the triple-lobe behavior is found in the I-V characteristics of some memristive devices generating another non-zero pinchoff point. In this paper, a flux-controlled memristive model is developed to generate the triple-lobe behavior (double pinchoff points) based on a fractional second-orde...
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| Format: | Article |
| Language: | English |
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IEEE
2018-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/8543141/ |
| _version_ | 1818924011078287360 |
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| author | Esraa M. Hamed Mohammed E. Fouda Abdullah G. Alharbi Ahmed G. Radwan |
| author_facet | Esraa M. Hamed Mohammed E. Fouda Abdullah G. Alharbi Ahmed G. Radwan |
| author_sort | Esraa M. Hamed |
| collection | DOAJ |
| description | Recently, the triple-lobe behavior is found in the I-V characteristics of some memristive devices generating another non-zero pinchoff point. In this paper, a flux-controlled memristive model is developed to generate the triple-lobe behavior (double pinchoff points) based on a fractional second-order model. The conditions for observing triple lobes are derived besides the coordinates of the pinchoff points. Different scenarios have been considered by changing the model parameters and fractional order. Furthermore, the minimum and maximum achievable conductances are analyzed and mathematically derived. In addition, a floating emulation circuit is introduced and analyzed, which is able to generate the triple-lobe behavior and mimic the dynamics of the proposed fractional modeling equation, showing good matching with the mathematical model. Finally, the obtained triple-lobe behaviors have been verified using experiments with fractional orders: 0.3 and 0.4. |
| first_indexed | 2024-12-20T02:18:32Z |
| format | Article |
| id | doaj.art-46bdba4eb3da4af9a15b56387c4b46b7 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-20T02:18:32Z |
| publishDate | 2018-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-46bdba4eb3da4af9a15b56387c4b46b72022-12-21T19:56:52ZengIEEEIEEE Access2169-35362018-01-016751697518010.1109/ACCESS.2018.28829428543141Experimental Verification of Triple Lobes Generation in Fractional Memristive CircuitsEsraa M. Hamed0Mohammed E. Fouda1https://orcid.org/0000-0001-7139-3428Abdullah G. Alharbi2Ahmed G. Radwan3https://orcid.org/0000-0002-6119-8482NISC, Nile University, Cairo, EgyptDepartment of Engineering Mathematics and Physics, Cairo University, Giza, EgyptDepartment of Electrical Engineering, Faculty of Engineering, Jouf University, Sakaka, Saudi ArabiaNISC, Nile University, Cairo, EgyptRecently, the triple-lobe behavior is found in the I-V characteristics of some memristive devices generating another non-zero pinchoff point. In this paper, a flux-controlled memristive model is developed to generate the triple-lobe behavior (double pinchoff points) based on a fractional second-order model. The conditions for observing triple lobes are derived besides the coordinates of the pinchoff points. Different scenarios have been considered by changing the model parameters and fractional order. Furthermore, the minimum and maximum achievable conductances are analyzed and mathematically derived. In addition, a floating emulation circuit is introduced and analyzed, which is able to generate the triple-lobe behavior and mimic the dynamics of the proposed fractional modeling equation, showing good matching with the mathematical model. Finally, the obtained triple-lobe behaviors have been verified using experiments with fractional orders: 0.3 and 0.4.https://ieeexplore.ieee.org/document/8543141/Fractional-order memristormemristorpinched hysteresistriple lobes |
| spellingShingle | Esraa M. Hamed Mohammed E. Fouda Abdullah G. Alharbi Ahmed G. Radwan Experimental Verification of Triple Lobes Generation in Fractional Memristive Circuits IEEE Access Fractional-order memristor memristor pinched hysteresis triple lobes |
| title | Experimental Verification of Triple Lobes Generation in Fractional Memristive Circuits |
| title_full | Experimental Verification of Triple Lobes Generation in Fractional Memristive Circuits |
| title_fullStr | Experimental Verification of Triple Lobes Generation in Fractional Memristive Circuits |
| title_full_unstemmed | Experimental Verification of Triple Lobes Generation in Fractional Memristive Circuits |
| title_short | Experimental Verification of Triple Lobes Generation in Fractional Memristive Circuits |
| title_sort | experimental verification of triple lobes generation in fractional memristive circuits |
| topic | Fractional-order memristor memristor pinched hysteresis triple lobes |
| url | https://ieeexplore.ieee.org/document/8543141/ |
| work_keys_str_mv | AT esraamhamed experimentalverificationoftriplelobesgenerationinfractionalmemristivecircuits AT mohammedefouda experimentalverificationoftriplelobesgenerationinfractionalmemristivecircuits AT abdullahgalharbi experimentalverificationoftriplelobesgenerationinfractionalmemristivecircuits AT ahmedgradwan experimentalverificationoftriplelobesgenerationinfractionalmemristivecircuits |