Software and DVFS Tuning for Performance and Energy-Efficiency on Intel KNL Processors
Energy consumption of processors and memories is quickly becoming a limiting factor in the deployment of large computing systems. For this reason, it is important to understand the energy performance of these processors and to study strategies allowing their use in the most efficient way. In this wo...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2018-06-01
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| Series: | Journal of Low Power Electronics and Applications |
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| Online Access: | http://www.mdpi.com/2079-9268/8/2/18 |
| _version_ | 1811262414295924736 |
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| author | Enrico Calore Alessandro Gabbana Sebastiano Fabio Schifano Raffaele Tripiccione |
| author_facet | Enrico Calore Alessandro Gabbana Sebastiano Fabio Schifano Raffaele Tripiccione |
| author_sort | Enrico Calore |
| collection | DOAJ |
| description | Energy consumption of processors and memories is quickly becoming a limiting factor in the deployment of large computing systems. For this reason, it is important to understand the energy performance of these processors and to study strategies allowing their use in the most efficient way. In this work, we focus on the computing and energy performance of the Knights Landing Xeon Phi, the latest Intel many-core architecture processor for HPC applications. We consider the 64-core Xeon Phi 7230 and profile its performance and energy efficiency using both its on-chip MCDRAM and the off-chip DDR4 memory as the main storage for application data. As a benchmark application, we use a lattice Boltzmann code heavily optimized for this architecture and implemented using several different arrangements of the application data in memory (data-layouts, in short). We also assess the dependence of energy consumption on data-layouts, memory configurations (DDR4 or MCDRAM) and the number of threads per core. We finally consider possible trade-offs between computing performance and energy efficiency, tuning the clock frequency of the processor using the Dynamic Voltage and Frequency Scaling (DVFS) technique. |
| first_indexed | 2024-04-12T19:24:49Z |
| format | Article |
| id | doaj.art-473ff22f66c34317824e443ddd724687 |
| institution | Directory Open Access Journal |
| issn | 2079-9268 |
| language | English |
| last_indexed | 2024-04-12T19:24:49Z |
| publishDate | 2018-06-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Journal of Low Power Electronics and Applications |
| spelling | doaj.art-473ff22f66c34317824e443ddd7246872022-12-22T03:19:30ZengMDPI AGJournal of Low Power Electronics and Applications2079-92682018-06-01821810.3390/jlpea8020018jlpea8020018Software and DVFS Tuning for Performance and Energy-Efficiency on Intel KNL ProcessorsEnrico Calore0Alessandro Gabbana1Sebastiano Fabio Schifano2Raffaele Tripiccione3Università degli Studi di Ferrara and INFN, 44122 Ferrara, ItalyUniversità degli Studi di Ferrara and INFN, 44122 Ferrara, ItalyUniversità degli Studi di Ferrara and INFN, 44122 Ferrara, ItalyUniversità degli Studi di Ferrara and INFN, 44122 Ferrara, ItalyEnergy consumption of processors and memories is quickly becoming a limiting factor in the deployment of large computing systems. For this reason, it is important to understand the energy performance of these processors and to study strategies allowing their use in the most efficient way. In this work, we focus on the computing and energy performance of the Knights Landing Xeon Phi, the latest Intel many-core architecture processor for HPC applications. We consider the 64-core Xeon Phi 7230 and profile its performance and energy efficiency using both its on-chip MCDRAM and the off-chip DDR4 memory as the main storage for application data. As a benchmark application, we use a lattice Boltzmann code heavily optimized for this architecture and implemented using several different arrangements of the application data in memory (data-layouts, in short). We also assess the dependence of energy consumption on data-layouts, memory configurations (DDR4 or MCDRAM) and the number of threads per core. We finally consider possible trade-offs between computing performance and energy efficiency, tuning the clock frequency of the processor using the Dynamic Voltage and Frequency Scaling (DVFS) technique.http://www.mdpi.com/2079-9268/8/2/18energyKNLMCDRAMmemorylattice BoltzmannHPCDVFS |
| spellingShingle | Enrico Calore Alessandro Gabbana Sebastiano Fabio Schifano Raffaele Tripiccione Software and DVFS Tuning for Performance and Energy-Efficiency on Intel KNL Processors Journal of Low Power Electronics and Applications energy KNL MCDRAM memory lattice Boltzmann HPC DVFS |
| title | Software and DVFS Tuning for Performance and Energy-Efficiency on Intel KNL Processors |
| title_full | Software and DVFS Tuning for Performance and Energy-Efficiency on Intel KNL Processors |
| title_fullStr | Software and DVFS Tuning for Performance and Energy-Efficiency on Intel KNL Processors |
| title_full_unstemmed | Software and DVFS Tuning for Performance and Energy-Efficiency on Intel KNL Processors |
| title_short | Software and DVFS Tuning for Performance and Energy-Efficiency on Intel KNL Processors |
| title_sort | software and dvfs tuning for performance and energy efficiency on intel knl processors |
| topic | energy KNL MCDRAM memory lattice Boltzmann HPC DVFS |
| url | http://www.mdpi.com/2079-9268/8/2/18 |
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