Efficient Dynamic Reconfigurable CNN Accelerator for Edge Intelligence Computing on FPGA
This paper proposes an efficient dynamic reconfigurable CNN accelerator (EDRCA) for FPGAs to tackle the issues of limited hardware resources and low energy efficiency in the deployment of convolutional neural networks on embedded edge computing devices. First, a configuration layer sequence optimiza...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2023-03-01
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| Series: | Information |
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| Online Access: | https://www.mdpi.com/2078-2489/14/3/194 |
| _version_ | 1797611088482664448 |
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| author | Kaisheng Shi Mingwei Wang Xin Tan Qianghua Li Tao Lei |
| author_facet | Kaisheng Shi Mingwei Wang Xin Tan Qianghua Li Tao Lei |
| author_sort | Kaisheng Shi |
| collection | DOAJ |
| description | This paper proposes an efficient dynamic reconfigurable CNN accelerator (EDRCA) for FPGAs to tackle the issues of limited hardware resources and low energy efficiency in the deployment of convolutional neural networks on embedded edge computing devices. First, a configuration layer sequence optimization method is proposed to minimize the configuration time overhead and improve performance. Second, accelerator templates for dynamic regions are designed to create a unified high-speed interface and enhance operational performance. The dynamic reconfigurable technology is applied on the Xilinx KV260 FPGA platform to design the EDRCA accelerator, resolving the hardware resource constraints in traditional accelerator design. The YOLOV2-TINY object detection network is used to test the EDRCA accelerator on the Xilinx KV260 platform using floating point data. Results at 250 MHz show a computing performance of 75.1929 GOPS, peak power consumption of 5.25 W, and power efficiency of 13.6219 GOPS/W, indicating the potential of the EDRCA accelerator for edge intelligence computing. |
| first_indexed | 2024-03-11T06:23:54Z |
| format | Article |
| id | doaj.art-477b3e467ab246c386810f224f06ccfd |
| institution | Directory Open Access Journal |
| issn | 2078-2489 |
| language | English |
| last_indexed | 2024-03-11T06:23:54Z |
| publishDate | 2023-03-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Information |
| spelling | doaj.art-477b3e467ab246c386810f224f06ccfd2023-11-17T11:44:24ZengMDPI AGInformation2078-24892023-03-0114319410.3390/info14030194Efficient Dynamic Reconfigurable CNN Accelerator for Edge Intelligence Computing on FPGAKaisheng Shi0Mingwei Wang1Xin Tan2Qianghua Li3Tao Lei4College of Electronic Information and Artificial Intelligence, Shaanxi University of Science and Technology, Xi’an 710021, ChinaCollege of Electronic Information and Artificial Intelligence, Shaanxi University of Science and Technology, Xi’an 710021, ChinaCollege of Electronic Information and Artificial Intelligence, Shaanxi University of Science and Technology, Xi’an 710021, ChinaCollege of Electrical and Control Engineering, Shaanxi University of Science and Technology, Xi’an 710021, ChinaCollege of Electronic Information and Artificial Intelligence, Shaanxi University of Science and Technology, Xi’an 710021, ChinaThis paper proposes an efficient dynamic reconfigurable CNN accelerator (EDRCA) for FPGAs to tackle the issues of limited hardware resources and low energy efficiency in the deployment of convolutional neural networks on embedded edge computing devices. First, a configuration layer sequence optimization method is proposed to minimize the configuration time overhead and improve performance. Second, accelerator templates for dynamic regions are designed to create a unified high-speed interface and enhance operational performance. The dynamic reconfigurable technology is applied on the Xilinx KV260 FPGA platform to design the EDRCA accelerator, resolving the hardware resource constraints in traditional accelerator design. The YOLOV2-TINY object detection network is used to test the EDRCA accelerator on the Xilinx KV260 platform using floating point data. Results at 250 MHz show a computing performance of 75.1929 GOPS, peak power consumption of 5.25 W, and power efficiency of 13.6219 GOPS/W, indicating the potential of the EDRCA accelerator for edge intelligence computing.https://www.mdpi.com/2078-2489/14/3/194FPGACNNdynamic reconfigurationhardware acceleratortarget detection |
| spellingShingle | Kaisheng Shi Mingwei Wang Xin Tan Qianghua Li Tao Lei Efficient Dynamic Reconfigurable CNN Accelerator for Edge Intelligence Computing on FPGA Information FPGA CNN dynamic reconfiguration hardware accelerator target detection |
| title | Efficient Dynamic Reconfigurable CNN Accelerator for Edge Intelligence Computing on FPGA |
| title_full | Efficient Dynamic Reconfigurable CNN Accelerator for Edge Intelligence Computing on FPGA |
| title_fullStr | Efficient Dynamic Reconfigurable CNN Accelerator for Edge Intelligence Computing on FPGA |
| title_full_unstemmed | Efficient Dynamic Reconfigurable CNN Accelerator for Edge Intelligence Computing on FPGA |
| title_short | Efficient Dynamic Reconfigurable CNN Accelerator for Edge Intelligence Computing on FPGA |
| title_sort | efficient dynamic reconfigurable cnn accelerator for edge intelligence computing on fpga |
| topic | FPGA CNN dynamic reconfiguration hardware accelerator target detection |
| url | https://www.mdpi.com/2078-2489/14/3/194 |
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