A PROPOSED METHOD OF IMPLEMENTATION OF AN OPTIMAL FAST AND VERY LOW COST ADDER BY USING XILINX FPGA
There are two man methods of design the digital adder circuits, First is the serial adder that implement using fill adders, this method has a lost and a low a low speed Second is the last parallel adder or the so-called fast kookabend adder that has twice speed of the serial adder and very high cos...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
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University of Baghdad
2003-06-01
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| Series: | Journal of Engineering |
| Subjects: | |
| Online Access: | https://www.joe.uobaghdad.edu.iq/index.php/main/article/view/2626 |
| _version_ | 1797266972346417152 |
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| author | w.a Mahmoud Dhafer R. Zaghar Mohannad K. Sabir |
| author_facet | w.a Mahmoud Dhafer R. Zaghar Mohannad K. Sabir |
| author_sort | w.a Mahmoud |
| collection | DOAJ |
| description |
There are two man methods of design the digital adder circuits, First is the serial adder that implement using fill adders, this method has a lost and a low a low speed Second is the last parallel adder or the so-called fast kookabend adder that has twice speed of the serial adder and very high cost Xilinx FPGA
modern IC used to implement high-speed digital circuits The opuntzation of speed and cost in design is achievel ming Xidens FPGA, which requires several rules that differ from that of optimization of Boolean algehea This paper shows the principle of the Xilins FPGA sechitecture as well the set of conditions of eptimal design, and proposes a new method of implementing a fast sidder with very low cost wing Xinx FPGA A 16-bit adder was used to show the applications of this method and comparison with two classical advantages of the proposed method are demonstrated through a a mume mumeric example.
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| first_indexed | 2024-03-07T15:36:34Z |
| format | Article |
| id | doaj.art-47e42c3dc4a8460583ca80c3e752e632 |
| institution | Directory Open Access Journal |
| issn | 1726-4073 2520-3339 |
| language | English |
| last_indexed | 2024-04-25T01:09:11Z |
| publishDate | 2003-06-01 |
| publisher | University of Baghdad |
| record_format | Article |
| series | Journal of Engineering |
| spelling | doaj.art-47e42c3dc4a8460583ca80c3e752e6322024-03-10T09:52:47ZengUniversity of BaghdadJournal of Engineering1726-40732520-33392003-06-0190210.31026/j.eng.2003.02.03A PROPOSED METHOD OF IMPLEMENTATION OF AN OPTIMAL FAST AND VERY LOW COST ADDER BY USING XILINX FPGAw.a Mahmoud Dhafer R. Zaghar Mohannad K. Sabir There are two man methods of design the digital adder circuits, First is the serial adder that implement using fill adders, this method has a lost and a low a low speed Second is the last parallel adder or the so-called fast kookabend adder that has twice speed of the serial adder and very high cost Xilinx FPGA modern IC used to implement high-speed digital circuits The opuntzation of speed and cost in design is achievel ming Xidens FPGA, which requires several rules that differ from that of optimization of Boolean algehea This paper shows the principle of the Xilins FPGA sechitecture as well the set of conditions of eptimal design, and proposes a new method of implementing a fast sidder with very low cost wing Xinx FPGA A 16-bit adder was used to show the applications of this method and comparison with two classical advantages of the proposed method are demonstrated through a a mume mumeric example. https://www.joe.uobaghdad.edu.iq/index.php/main/article/view/2626DSP, synchronous, asynchronous, short processing time, FPGA, Xilinx, Virtex, CLB, digital adder, serial adder, fast parallel adder |
| spellingShingle | w.a Mahmoud Dhafer R. Zaghar Mohannad K. Sabir A PROPOSED METHOD OF IMPLEMENTATION OF AN OPTIMAL FAST AND VERY LOW COST ADDER BY USING XILINX FPGA Journal of Engineering DSP, synchronous, asynchronous, short processing time, FPGA, Xilinx, Virtex, CLB, digital adder, serial adder, fast parallel adder |
| title | A PROPOSED METHOD OF IMPLEMENTATION OF AN OPTIMAL FAST AND VERY LOW COST ADDER BY USING XILINX FPGA |
| title_full | A PROPOSED METHOD OF IMPLEMENTATION OF AN OPTIMAL FAST AND VERY LOW COST ADDER BY USING XILINX FPGA |
| title_fullStr | A PROPOSED METHOD OF IMPLEMENTATION OF AN OPTIMAL FAST AND VERY LOW COST ADDER BY USING XILINX FPGA |
| title_full_unstemmed | A PROPOSED METHOD OF IMPLEMENTATION OF AN OPTIMAL FAST AND VERY LOW COST ADDER BY USING XILINX FPGA |
| title_short | A PROPOSED METHOD OF IMPLEMENTATION OF AN OPTIMAL FAST AND VERY LOW COST ADDER BY USING XILINX FPGA |
| title_sort | proposed method of implementation of an optimal fast and very low cost adder by using xilinx fpga |
| topic | DSP, synchronous, asynchronous, short processing time, FPGA, Xilinx, Virtex, CLB, digital adder, serial adder, fast parallel adder |
| url | https://www.joe.uobaghdad.edu.iq/index.php/main/article/view/2626 |
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