An Optimized Flexible Accelerator for Elliptic Curve Point Multiplication over NIST Binary Fields
This article proposes a flexible hardware accelerator optimized from a throughput and area point of view for the computationally intensive part of elliptic curve cryptography. The target binary fields, defined by the National Institute of Standards and Technology, are <inline-formula><math...
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| Format: | Article |
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MDPI AG
2023-09-01
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| Series: | Applied Sciences |
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| Online Access: | https://www.mdpi.com/2076-3417/13/19/10882 |
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| author | Amer Aljaedi Muhammad Rashid Sajjad Shaukat Jamal Adel R. Alharbi Mohammed Alotaibi |
| author_facet | Amer Aljaedi Muhammad Rashid Sajjad Shaukat Jamal Adel R. Alharbi Mohammed Alotaibi |
| author_sort | Amer Aljaedi |
| collection | DOAJ |
| description | This article proposes a flexible hardware accelerator optimized from a throughput and area point of view for the computationally intensive part of elliptic curve cryptography. The target binary fields, defined by the National Institute of Standards and Technology, are <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>G</mi><mi>F</mi><mo>(</mo><msup><mn>2</mn><mn>163</mn></msup><mo>)</mo></mrow></semantics></math></inline-formula>, <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>G</mi><mi>F</mi><mo>(</mo><msup><mn>2</mn><mn>233</mn></msup><mo>)</mo></mrow></semantics></math></inline-formula>, <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>G</mi><mi>F</mi><mo>(</mo><msup><mn>2</mn><mn>283</mn></msup><mo>)</mo></mrow></semantics></math></inline-formula>, <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>G</mi><mi>F</mi><mo>(</mo><msup><mn>2</mn><mn>409</mn></msup><mo>)</mo></mrow></semantics></math></inline-formula>, and <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>G</mi><mi>F</mi><mo>(</mo><msup><mn>2</mn><mn>571</mn></msup><mo>)</mo></mrow></semantics></math></inline-formula>. For the optimization of throughput, the proposed accelerator employs a digit-parallel multiplier. The size of the digit is 41 bits. The proposed accelerator has reused the multiplication and squaring circuit for area optimization to compute modular inversions. Flexibility is included using three additional buffers on top of the proposed accelerator architecture to load different input parameters. Finally, a dedicated controller is used to optimize control signal handling. The architecture is modeled using Verilog and implemented up to the post-place-and-route level on a Xilinx Virtex-7 field-programmable gate array. The area utilization of our accelerator in slices is 1479, 1998, 2573, 3271, and 4469 for <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>m</mi><mo>=</mo><mn>163</mn></mrow></semantics></math></inline-formula> to 571. The time needed to perform one-point multiplication is 7.15, 10.60, 13.26, 20.96, and 30.42 μs. Similarly, the throughput over area figures for the same key lengths are 94.56, 47.21, 29.30, 14.58, and 7.35. Consequently, achieved results and a comprehensive performance comparison show the suitability of the proposed design for constrained environments that demand throughput/area-efficient implementations. |
| first_indexed | 2024-03-10T21:48:29Z |
| format | Article |
| id | doaj.art-481e450eb9b949aba7e90c0d50e2d6d4 |
| institution | Directory Open Access Journal |
| issn | 2076-3417 |
| language | English |
| last_indexed | 2024-03-10T21:48:29Z |
| publishDate | 2023-09-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Applied Sciences |
| spelling | doaj.art-481e450eb9b949aba7e90c0d50e2d6d42023-11-19T14:05:27ZengMDPI AGApplied Sciences2076-34172023-09-0113191088210.3390/app131910882An Optimized Flexible Accelerator for Elliptic Curve Point Multiplication over NIST Binary FieldsAmer Aljaedi0Muhammad Rashid1Sajjad Shaukat Jamal2Adel R. Alharbi3Mohammed Alotaibi4College of Computing and Information Technology, University of Tabuk, Tabuk 71491, Saudi ArabiaComputer Engineering Department, Umm Al Qura University, Makkah 21955, Saudi ArabiaDepartment of Mathematics, College of Science, King Khalid University, Abha 61413, Saudi ArabiaCollege of Computing and Information Technology, University of Tabuk, Tabuk 71491, Saudi ArabiaDepartment of Management Information Systems, College of Business Administration, University of Tabuk, Tabuk 71491, Saudi ArabiaThis article proposes a flexible hardware accelerator optimized from a throughput and area point of view for the computationally intensive part of elliptic curve cryptography. The target binary fields, defined by the National Institute of Standards and Technology, are <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>G</mi><mi>F</mi><mo>(</mo><msup><mn>2</mn><mn>163</mn></msup><mo>)</mo></mrow></semantics></math></inline-formula>, <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>G</mi><mi>F</mi><mo>(</mo><msup><mn>2</mn><mn>233</mn></msup><mo>)</mo></mrow></semantics></math></inline-formula>, <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>G</mi><mi>F</mi><mo>(</mo><msup><mn>2</mn><mn>283</mn></msup><mo>)</mo></mrow></semantics></math></inline-formula>, <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>G</mi><mi>F</mi><mo>(</mo><msup><mn>2</mn><mn>409</mn></msup><mo>)</mo></mrow></semantics></math></inline-formula>, and <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>G</mi><mi>F</mi><mo>(</mo><msup><mn>2</mn><mn>571</mn></msup><mo>)</mo></mrow></semantics></math></inline-formula>. For the optimization of throughput, the proposed accelerator employs a digit-parallel multiplier. The size of the digit is 41 bits. The proposed accelerator has reused the multiplication and squaring circuit for area optimization to compute modular inversions. Flexibility is included using three additional buffers on top of the proposed accelerator architecture to load different input parameters. Finally, a dedicated controller is used to optimize control signal handling. The architecture is modeled using Verilog and implemented up to the post-place-and-route level on a Xilinx Virtex-7 field-programmable gate array. The area utilization of our accelerator in slices is 1479, 1998, 2573, 3271, and 4469 for <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>m</mi><mo>=</mo><mn>163</mn></mrow></semantics></math></inline-formula> to 571. The time needed to perform one-point multiplication is 7.15, 10.60, 13.26, 20.96, and 30.42 μs. Similarly, the throughput over area figures for the same key lengths are 94.56, 47.21, 29.30, 14.58, and 7.35. Consequently, achieved results and a comprehensive performance comparison show the suitability of the proposed design for constrained environments that demand throughput/area-efficient implementations.https://www.mdpi.com/2076-3417/13/19/10882hardwareacceleratorelliptic curve cryptographypoint multiplicationFPGA |
| spellingShingle | Amer Aljaedi Muhammad Rashid Sajjad Shaukat Jamal Adel R. Alharbi Mohammed Alotaibi An Optimized Flexible Accelerator for Elliptic Curve Point Multiplication over NIST Binary Fields Applied Sciences hardware accelerator elliptic curve cryptography point multiplication FPGA |
| title | An Optimized Flexible Accelerator for Elliptic Curve Point Multiplication over NIST Binary Fields |
| title_full | An Optimized Flexible Accelerator for Elliptic Curve Point Multiplication over NIST Binary Fields |
| title_fullStr | An Optimized Flexible Accelerator for Elliptic Curve Point Multiplication over NIST Binary Fields |
| title_full_unstemmed | An Optimized Flexible Accelerator for Elliptic Curve Point Multiplication over NIST Binary Fields |
| title_short | An Optimized Flexible Accelerator for Elliptic Curve Point Multiplication over NIST Binary Fields |
| title_sort | optimized flexible accelerator for elliptic curve point multiplication over nist binary fields |
| topic | hardware accelerator elliptic curve cryptography point multiplication FPGA |
| url | https://www.mdpi.com/2076-3417/13/19/10882 |
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