CMOS Technology for Increasing Efficiency of Clock Gating Techniques Using Tri-State Buffer

CMOS Technology for Increasing Efficiency of Clock Gating Techniques Using Tri-State Buffer

Clock gating is an effective technique of decreasing dynamic power dissipation in synchronous design. One of the methods used to realize this goal is to mask the clock which goes to the unnecessary to use in specific time. This paper will present a comparative analysis of this clock gating technique...

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Bibliographic Details
Main Authors: Maan HAMEED, Asem KHMAG, Fakhrul ZAMAN, Abdurrahman RAMLI
Format: Article
Language:English
Published: Walailak University 2016-01-01
Series:Walailak Journal of Science and Technology
Subjects:
Clock gating
power dissipation
dynamic power
low power
tri-state techniques
ALU
Online Access:http://wjst.wu.ac.th/index.php/wjst/article/view/1992

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