An Efficient RTL Design for a Wearable Brain–Computer Interface
This article proposes an efficient and accurate embedded motor imagery-based brain–computer interface (MI-BCI) that meets the requirements for wearable and real-time applications. To achieve a suitable accuracy considering hardware constraints, we explore BCI transducer algorithms, among which Infin...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Hindawi-IET
2024-01-01
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| Series: | IET Computers & Digital Techniques |
| Online Access: | http://dx.doi.org/10.1049/2024/5596468 |
| _version_ | 1797260537965314048 |
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| author | Tahereh Vasei Mohammad Ali Saber Alireza Nahvy Zainalabedin Navabi |
| author_facet | Tahereh Vasei Mohammad Ali Saber Alireza Nahvy Zainalabedin Navabi |
| author_sort | Tahereh Vasei |
| collection | DOAJ |
| description | This article proposes an efficient and accurate embedded motor imagery-based brain–computer interface (MI-BCI) that meets the requirements for wearable and real-time applications. To achieve a suitable accuracy considering hardware constraints, we explore BCI transducer algorithms, among which Infinite impulse response (IIR) filter, common spatial pattern, and support vector machine are used to preprocess, extract features, and classify data, respectively. With our hardware implementation of these tasks, we have achieved an accuracy of 77%. Our system is designed at register transfer level (RTL) targeting an ASIC implementation, which significantly decreases power consumption, latency, and area compared to the state-of-the-art (SoA) architectures for embedded BCI systems. To this end, we fold IIR filters using time-shared and RAM-based techniques and use hardware-friendly algorithms for the implementation of other tasks. The RTL design is realized on 45 nm CMOS technology consuming 4 mW power and 0.25 mm2 area, which outperforms the SoA platforms for embedded BCI systems. To further illustrate the outperformance of our design, the proposed architecture is implemented on Virtex-7 field program gate array as a prototyping platform consuming 6 μJ energy with 1.52% area utilization. |
| first_indexed | 2024-04-24T23:26:54Z |
| format | Article |
| id | doaj.art-488524fe637c45c29dc4b66573d41361 |
| institution | Directory Open Access Journal |
| issn | 1751-861X |
| language | English |
| last_indexed | 2024-04-24T23:26:54Z |
| publishDate | 2024-01-01 |
| publisher | Hindawi-IET |
| record_format | Article |
| series | IET Computers & Digital Techniques |
| spelling | doaj.art-488524fe637c45c29dc4b66573d413612024-03-16T00:00:02ZengHindawi-IETIET Computers & Digital Techniques1751-861X2024-01-01202410.1049/2024/5596468An Efficient RTL Design for a Wearable Brain–Computer InterfaceTahereh Vasei0Mohammad Ali Saber1Alireza Nahvy2Zainalabedin Navabi3School of Electrical and Computer EngineeringSchool of Electrical and Computer EngineeringSchool of Electrical and Computer EngineeringSchool of Electrical and Computer EngineeringThis article proposes an efficient and accurate embedded motor imagery-based brain–computer interface (MI-BCI) that meets the requirements for wearable and real-time applications. To achieve a suitable accuracy considering hardware constraints, we explore BCI transducer algorithms, among which Infinite impulse response (IIR) filter, common spatial pattern, and support vector machine are used to preprocess, extract features, and classify data, respectively. With our hardware implementation of these tasks, we have achieved an accuracy of 77%. Our system is designed at register transfer level (RTL) targeting an ASIC implementation, which significantly decreases power consumption, latency, and area compared to the state-of-the-art (SoA) architectures for embedded BCI systems. To this end, we fold IIR filters using time-shared and RAM-based techniques and use hardware-friendly algorithms for the implementation of other tasks. The RTL design is realized on 45 nm CMOS technology consuming 4 mW power and 0.25 mm2 area, which outperforms the SoA platforms for embedded BCI systems. To further illustrate the outperformance of our design, the proposed architecture is implemented on Virtex-7 field program gate array as a prototyping platform consuming 6 μJ energy with 1.52% area utilization.http://dx.doi.org/10.1049/2024/5596468 |
| spellingShingle | Tahereh Vasei Mohammad Ali Saber Alireza Nahvy Zainalabedin Navabi An Efficient RTL Design for a Wearable Brain–Computer Interface IET Computers & Digital Techniques |
| title | An Efficient RTL Design for a Wearable Brain–Computer Interface |
| title_full | An Efficient RTL Design for a Wearable Brain–Computer Interface |
| title_fullStr | An Efficient RTL Design for a Wearable Brain–Computer Interface |
| title_full_unstemmed | An Efficient RTL Design for a Wearable Brain–Computer Interface |
| title_short | An Efficient RTL Design for a Wearable Brain–Computer Interface |
| title_sort | efficient rtl design for a wearable brain computer interface |
| url | http://dx.doi.org/10.1049/2024/5596468 |
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