Gate-Level Static Approximate Adders: A Comparative Analysis
Approximate or inaccurate addition is found to be viable for practical applications which have an inherent error tolerance. Approximate addition is realized using an approximate adder, and many approximate adder designs have been put forward in the literature targeting an acceptable trade-off betwee...
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-11-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/10/23/2917 |
| _version_ | 1797507908480532480 |
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| author | Padmanabhan Balasubramanian Raunaq Nayar Douglas L. Maskell |
| author_facet | Padmanabhan Balasubramanian Raunaq Nayar Douglas L. Maskell |
| author_sort | Padmanabhan Balasubramanian |
| collection | DOAJ |
| description | Approximate or inaccurate addition is found to be viable for practical applications which have an inherent error tolerance. Approximate addition is realized using an approximate adder, and many approximate adder designs have been put forward in the literature targeting an acceptable trade-off between quality of results and savings in design metrics compared to the accurate adder. Approximate adders can be classified into three categories as: (a) suitable for FPGA implementation, (b) suitable for ASIC type implementation, and (c) suitable for FPGA and ASIC type implementations. Among these, approximate adders, which are suitable for FPGA and ASIC type implementations are particularly interesting given their versatility and they are typically designed at the gate level. Depending on the way approximation is built into an approximate adder, approximate adders can be classified into two kinds as static approximate adders and dynamic approximate adders. This paper compares and analyzes static approximate adders which are suitable for both FPGA and ASIC type implementations. We consider many static approximate adders and evaluate their performance for a digital image processing application using standard figures of merit such as peak signal to noise ratio and structural similarity index metric. We provide the error metrics of approximate adders, and the design metrics of accurate and approximate adders corresponding to FPGA and ASIC type implementations. For the FPGA implementation, we considered a Xilinx Artix-7 FPGA, and for an ASIC type implementation, we considered a 32/28 nm CMOS standard digital cell library. While the inferences from this work could serve as a useful reference to determine an optimum static approximate adder for a practical application, in particular, we found approximate adders HOAANED, HERLOA and M-HERLOA to be preferable. |
| first_indexed | 2024-03-10T04:55:08Z |
| format | Article |
| id | doaj.art-48f9c209725c4d06a94afb855f902273 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-10T04:55:08Z |
| publishDate | 2021-11-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-48f9c209725c4d06a94afb855f9022732023-11-23T02:16:02ZengMDPI AGElectronics2079-92922021-11-011023291710.3390/electronics10232917Gate-Level Static Approximate Adders: A Comparative AnalysisPadmanabhan Balasubramanian0Raunaq Nayar1Douglas L. Maskell2School of Computer Science and Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798, SingaporeSchool of Computer Science and Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798, SingaporeSchool of Computer Science and Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798, SingaporeApproximate or inaccurate addition is found to be viable for practical applications which have an inherent error tolerance. Approximate addition is realized using an approximate adder, and many approximate adder designs have been put forward in the literature targeting an acceptable trade-off between quality of results and savings in design metrics compared to the accurate adder. Approximate adders can be classified into three categories as: (a) suitable for FPGA implementation, (b) suitable for ASIC type implementation, and (c) suitable for FPGA and ASIC type implementations. Among these, approximate adders, which are suitable for FPGA and ASIC type implementations are particularly interesting given their versatility and they are typically designed at the gate level. Depending on the way approximation is built into an approximate adder, approximate adders can be classified into two kinds as static approximate adders and dynamic approximate adders. This paper compares and analyzes static approximate adders which are suitable for both FPGA and ASIC type implementations. We consider many static approximate adders and evaluate their performance for a digital image processing application using standard figures of merit such as peak signal to noise ratio and structural similarity index metric. We provide the error metrics of approximate adders, and the design metrics of accurate and approximate adders corresponding to FPGA and ASIC type implementations. For the FPGA implementation, we considered a Xilinx Artix-7 FPGA, and for an ASIC type implementation, we considered a 32/28 nm CMOS standard digital cell library. While the inferences from this work could serve as a useful reference to determine an optimum static approximate adder for a practical application, in particular, we found approximate adders HOAANED, HERLOA and M-HERLOA to be preferable.https://www.mdpi.com/2079-9292/10/23/2917approximate computingapproximate adderdigital circuitslogic designFPGAASIC |
| spellingShingle | Padmanabhan Balasubramanian Raunaq Nayar Douglas L. Maskell Gate-Level Static Approximate Adders: A Comparative Analysis Electronics approximate computing approximate adder digital circuits logic design FPGA ASIC |
| title | Gate-Level Static Approximate Adders: A Comparative Analysis |
| title_full | Gate-Level Static Approximate Adders: A Comparative Analysis |
| title_fullStr | Gate-Level Static Approximate Adders: A Comparative Analysis |
| title_full_unstemmed | Gate-Level Static Approximate Adders: A Comparative Analysis |
| title_short | Gate-Level Static Approximate Adders: A Comparative Analysis |
| title_sort | gate level static approximate adders a comparative analysis |
| topic | approximate computing approximate adder digital circuits logic design FPGA ASIC |
| url | https://www.mdpi.com/2079-9292/10/23/2917 |
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