Latency-Optimized Design of Data Bus Inversion
This paper proposes two new encoders for data bus inversion (DBI), which conventionally uses a majority voter to pick a data representation that minimizes switching activities and thus reduces the corresponding energy consumption. The new encoders employ simpler approximate voters comprising only tw...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-04-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/11/8/1205 |
| _version_ | 1797446683177517056 |
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| author | Sung-il Pae Kon-Woo Kwon |
| author_facet | Sung-il Pae Kon-Woo Kwon |
| author_sort | Sung-il Pae |
| collection | DOAJ |
| description | This paper proposes two new encoders for data bus inversion (DBI), which conventionally uses a majority voter to pick a data representation that minimizes switching activities and thus reduces the corresponding energy consumption. The new encoders employ simpler approximate voters comprising only two gate levels, which improve latency more than twice while still achieving switching activity savings by 9% and 11%, respectively. Although the proposed voters are not always accurate, the errors in the voters do not affect the correctness of data movement. We report various metrics, including latencies, areas, and operating powers, regarding five different designs, two proposed designs along with three conventional designs, based on 65-nm process implementations. |
| first_indexed | 2024-03-09T13:45:05Z |
| format | Article |
| id | doaj.art-49d9f50fb0c741cfa702ec3f05a168f8 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-09T13:45:05Z |
| publishDate | 2022-04-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-49d9f50fb0c741cfa702ec3f05a168f82023-11-30T21:01:51ZengMDPI AGElectronics2079-92922022-04-01118120510.3390/electronics11081205Latency-Optimized Design of Data Bus InversionSung-il Pae0Kon-Woo Kwon1Department of Computer Engineering, Hongik University, Seoul 04066, KoreaDepartment of Computer Engineering, Hongik University, Seoul 04066, KoreaThis paper proposes two new encoders for data bus inversion (DBI), which conventionally uses a majority voter to pick a data representation that minimizes switching activities and thus reduces the corresponding energy consumption. The new encoders employ simpler approximate voters comprising only two gate levels, which improve latency more than twice while still achieving switching activity savings by 9% and 11%, respectively. Although the proposed voters are not always accurate, the errors in the voters do not affect the correctness of data movement. We report various metrics, including latencies, areas, and operating powers, regarding five different designs, two proposed designs along with three conventional designs, based on 65-nm process implementations.https://www.mdpi.com/2079-9292/11/8/1205approximationdata bus inversionlatencymajority voterpower savingswitching activity |
| spellingShingle | Sung-il Pae Kon-Woo Kwon Latency-Optimized Design of Data Bus Inversion Electronics approximation data bus inversion latency majority voter power saving switching activity |
| title | Latency-Optimized Design of Data Bus Inversion |
| title_full | Latency-Optimized Design of Data Bus Inversion |
| title_fullStr | Latency-Optimized Design of Data Bus Inversion |
| title_full_unstemmed | Latency-Optimized Design of Data Bus Inversion |
| title_short | Latency-Optimized Design of Data Bus Inversion |
| title_sort | latency optimized design of data bus inversion |
| topic | approximation data bus inversion latency majority voter power saving switching activity |
| url | https://www.mdpi.com/2079-9292/11/8/1205 |
| work_keys_str_mv | AT sungilpae latencyoptimizeddesignofdatabusinversion AT konwookwon latencyoptimizeddesignofdatabusinversion |