A low complexity digital frequency calibration with high jitter immunity for ultra-low-power oscillators
<p>This paper presents a highly efficient digital frequency calibration method for ultra-low-power oscillators in wireless communication systems. This calibration method locks the ultra-low-power oscillator's output frequency to the reference clock of the wireless transceiver during its s...
| Main Authors: | , , |
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| Format: | Article |
| Language: | deu |
| Published: |
Copernicus Publications
2019-09-01
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| Series: | Advances in Radio Science |
| Online Access: | https://www.adv-radio-sci.net/17/145/2019/ars-17-145-2019.pdf |
| Summary: | <p>This paper presents a highly efficient digital frequency calibration method for ultra-low-power oscillators in wireless communication systems.
This calibration method locks the ultra-low-power oscillator's output frequency to the reference clock of the wireless transceiver during its send- and receive-state to achieve frequency stability over process variation and temperature drifts.
The introduced calibration scheme offers high jitter immunity and short locking periods overcoming frequency calibration errors for typical ultra-low-power oscillator's by utilizing non-linear segmented feedback levels.
In measurements the proposed calibration method improves the frequency stability of an ultra-low-power 32 kHz oscillator from 53 to 10 ppm <span class="inline-formula"><sup>∘</sup></span>C<span class="inline-formula"><sup>−1</sup></span> over a wide temperature range for temperature drifts of less than 1 <span class="inline-formula"><sup>∘</sup></span>C s<span class="inline-formula"><sup>−1</sup></span> with an estimated power consumption of 185 nW while coping with relocking periods of 7 ms.</p> |
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| ISSN: | 1684-9965 1684-9973 |