Optimal Common-Mode Voltage Injection for Phase-Modular Three-Phase PFC Rectifiers Minimizing Energy Buffering Requirement
Realizing an isolated three-phase Power Factor Correction (PFC) ac-dc converter as a phase-modular system, i.e., by star-connecting three single-phase PFC rectifier front-ends with individual isolated dc-dc converter stages generating a common dc output voltage advantageously facilitates the use of...
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| Format: | Article |
| Language: | English |
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IEEE
2023-01-01
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| Series: | IEEE Open Journal of Power Electronics |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10232379/ |
| _version_ | 1797685361158127616 |
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| author | David Menzi Valentin Marugg Thomas Langbauer Johann W. Kolar |
| author_facet | David Menzi Valentin Marugg Thomas Langbauer Johann W. Kolar |
| author_sort | David Menzi |
| collection | DOAJ |
| description | Realizing an isolated three-phase Power Factor Correction (PFC) ac-dc converter as a phase-modular system, i.e., by star-connecting three single-phase PFC rectifier front-ends with individual isolated dc-dc converter stages generating a common dc output voltage advantageously facilitates the use of standard single-phase converter modules. Further the low dc-link voltage level of typically <inline-formula><tex-math notation="LaTeX">$400 \,{\rm {V}}$</tex-math></inline-formula> (for a grid with <inline-formula><tex-math notation="LaTeX">$230 \,{\rm {V}}_{\rm{rms}}$</tex-math></inline-formula> line-to-neutral voltage) allows to employ high performance <inline-formula><tex-math notation="LaTeX">$600 \,{\rm {V}}$</tex-math></inline-formula> power semiconductors. The main drawback of this concept, however, is the fact that the time-varying single-phase input power only sums to a constant three-phase output power at the isolated dc output, such that large dc-link capacitor values are required in each module (in the range of several <inline-formula><tex-math notation="LaTeX">$100 \,{\mu }{\rm{F}}$</tex-math></inline-formula> for a <inline-formula><tex-math notation="LaTeX">$6 \,{\rm{kW}}$</tex-math></inline-formula> system), thereby limiting the achievable power density. It is known from literature that the dc-link energy buffering requirement <inline-formula><tex-math notation="LaTeX">$ {\Delta} {E}_{\rm{dc}}$</tex-math></inline-formula> can be reduced by means of a third-harmonic common-mode (CM) voltage injection modulation and this article identifies the optimal CM voltage waveform with respect to minimizing <inline-formula><tex-math notation="LaTeX">$ {\Delta} {E}_{\rm{dc}}$</tex-math></inline-formula>, i.e., reducing <inline-formula><tex-math notation="LaTeX">$ {\Delta} {E}_{\rm{dc}}$</tex-math></inline-formula> to the theoretical minimum by combining a brute-force evaluation of the time-domain CM voltage waveform with phase-symmetry considerations. Additionally, converter operation with minimum dc-link voltage and/or dc-link capacitor values is analyzed and a saturable grid current controller allowing operation of the PFC rectifier front-ends with the optimal CM voltage waveform is investigated. Experimental results with a <inline-formula><tex-math notation="LaTeX">$6 \,{\rm{kW}}$</tex-math></inline-formula> prototype system yield a reduction in <inline-formula><tex-math notation="LaTeX">$ {\Delta} {E}_{\rm{dc}}$</tex-math></inline-formula> by up to <inline-formula><tex-math notation="LaTeX">$42{\%}$</tex-math></inline-formula> (compared to conventional sinusoidal modulation), which closely matches the theoretical prediction. Also, PFC rectifier operation with a dc-link voltage level as low as <inline-formula><tex-math notation="LaTeX">$285 \,{\rm {V}}$</tex-math></inline-formula> (i.e., below the <inline-formula><tex-math notation="LaTeX">$325 \,{\rm {V}}_\mathrm{pk}$</tex-math></inline-formula> grid line-to-neutral voltage amplitude) and with ultra-low dc-link capacitor values is demonstrated. |
| first_indexed | 2024-03-12T00:43:04Z |
| format | Article |
| id | doaj.art-4aa87611b2ec4e238171f940a54b06b1 |
| institution | Directory Open Access Journal |
| issn | 2644-1314 |
| language | English |
| last_indexed | 2024-03-12T00:43:04Z |
| publishDate | 2023-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of Power Electronics |
| spelling | doaj.art-4aa87611b2ec4e238171f940a54b06b12023-09-14T23:01:54ZengIEEEIEEE Open Journal of Power Electronics2644-13142023-01-01467468610.1109/OJPEL.2023.330890410232379Optimal Common-Mode Voltage Injection for Phase-Modular Three-Phase PFC Rectifiers Minimizing Energy Buffering RequirementDavid Menzi0https://orcid.org/0000-0002-9562-2157Valentin Marugg1Thomas Langbauer2https://orcid.org/0000-0003-3248-0531Johann W. Kolar3https://orcid.org/0000-0002-6000-7402Power Electronic Systems Lab (PES), ETH Zurich, Zurich, SwitzerlandPower Electronic Systems Lab (PES), ETH Zurich, Zurich, SwitzerlandDivision Power Electronics, Silicon Austria Labs GmbH (SAL), Graz, AustriaPower Electronic Systems Lab (PES), ETH Zurich, Zurich, SwitzerlandRealizing an isolated three-phase Power Factor Correction (PFC) ac-dc converter as a phase-modular system, i.e., by star-connecting three single-phase PFC rectifier front-ends with individual isolated dc-dc converter stages generating a common dc output voltage advantageously facilitates the use of standard single-phase converter modules. Further the low dc-link voltage level of typically <inline-formula><tex-math notation="LaTeX">$400 \,{\rm {V}}$</tex-math></inline-formula> (for a grid with <inline-formula><tex-math notation="LaTeX">$230 \,{\rm {V}}_{\rm{rms}}$</tex-math></inline-formula> line-to-neutral voltage) allows to employ high performance <inline-formula><tex-math notation="LaTeX">$600 \,{\rm {V}}$</tex-math></inline-formula> power semiconductors. The main drawback of this concept, however, is the fact that the time-varying single-phase input power only sums to a constant three-phase output power at the isolated dc output, such that large dc-link capacitor values are required in each module (in the range of several <inline-formula><tex-math notation="LaTeX">$100 \,{\mu }{\rm{F}}$</tex-math></inline-formula> for a <inline-formula><tex-math notation="LaTeX">$6 \,{\rm{kW}}$</tex-math></inline-formula> system), thereby limiting the achievable power density. It is known from literature that the dc-link energy buffering requirement <inline-formula><tex-math notation="LaTeX">$ {\Delta} {E}_{\rm{dc}}$</tex-math></inline-formula> can be reduced by means of a third-harmonic common-mode (CM) voltage injection modulation and this article identifies the optimal CM voltage waveform with respect to minimizing <inline-formula><tex-math notation="LaTeX">$ {\Delta} {E}_{\rm{dc}}$</tex-math></inline-formula>, i.e., reducing <inline-formula><tex-math notation="LaTeX">$ {\Delta} {E}_{\rm{dc}}$</tex-math></inline-formula> to the theoretical minimum by combining a brute-force evaluation of the time-domain CM voltage waveform with phase-symmetry considerations. Additionally, converter operation with minimum dc-link voltage and/or dc-link capacitor values is analyzed and a saturable grid current controller allowing operation of the PFC rectifier front-ends with the optimal CM voltage waveform is investigated. Experimental results with a <inline-formula><tex-math notation="LaTeX">$6 \,{\rm{kW}}$</tex-math></inline-formula> prototype system yield a reduction in <inline-formula><tex-math notation="LaTeX">$ {\Delta} {E}_{\rm{dc}}$</tex-math></inline-formula> by up to <inline-formula><tex-math notation="LaTeX">$42{\%}$</tex-math></inline-formula> (compared to conventional sinusoidal modulation), which closely matches the theoretical prediction. Also, PFC rectifier operation with a dc-link voltage level as low as <inline-formula><tex-math notation="LaTeX">$285 \,{\rm {V}}$</tex-math></inline-formula> (i.e., below the <inline-formula><tex-math notation="LaTeX">$325 \,{\rm {V}}_\mathrm{pk}$</tex-math></inline-formula> grid line-to-neutral voltage amplitude) and with ultra-low dc-link capacitor values is demonstrated.https://ieeexplore.ieee.org/document/10232379/Ac-dc converterthree-phasePFC rectifiermodularharmonic injectionzero sequence |
| spellingShingle | David Menzi Valentin Marugg Thomas Langbauer Johann W. Kolar Optimal Common-Mode Voltage Injection for Phase-Modular Three-Phase PFC Rectifiers Minimizing Energy Buffering Requirement IEEE Open Journal of Power Electronics Ac-dc converter three-phase PFC rectifier modular harmonic injection zero sequence |
| title | Optimal Common-Mode Voltage Injection for Phase-Modular Three-Phase PFC Rectifiers Minimizing Energy Buffering Requirement |
| title_full | Optimal Common-Mode Voltage Injection for Phase-Modular Three-Phase PFC Rectifiers Minimizing Energy Buffering Requirement |
| title_fullStr | Optimal Common-Mode Voltage Injection for Phase-Modular Three-Phase PFC Rectifiers Minimizing Energy Buffering Requirement |
| title_full_unstemmed | Optimal Common-Mode Voltage Injection for Phase-Modular Three-Phase PFC Rectifiers Minimizing Energy Buffering Requirement |
| title_short | Optimal Common-Mode Voltage Injection for Phase-Modular Three-Phase PFC Rectifiers Minimizing Energy Buffering Requirement |
| title_sort | optimal common mode voltage injection for phase modular three phase pfc rectifiers minimizing energy buffering requirement |
| topic | Ac-dc converter three-phase PFC rectifier modular harmonic injection zero sequence |
| url | https://ieeexplore.ieee.org/document/10232379/ |
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