A Low Voltage Low Power CMOS Implementation of Second Generation Orderly Current Buffer
In this paper, a novel low voltage low power current buffer was presented. The proposed structure was implemented in CMOS technology and is the second generation of OCB (orderly current buffer) called OCBII. This generation is arranged in single input-single output configuration and has modular stru...
| Autors principals: | , |
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| Format: | Article |
| Idioma: | English |
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Iran University of Science and Technology
2019-06-01
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| Col·lecció: | Iranian Journal of Electrical and Electronic Engineering |
| Matèries: | |
| Accés en línia: | http://ijeee.iust.ac.ir/browse.php?a_code=A-10-46-4&slc_lang=en&sid=1 |
| _version_ | 1829487353778929664 |
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| author | S. J. Azhari M. Zareie |
| author_facet | S. J. Azhari M. Zareie |
| author_sort | S. J. Azhari |
| collection | DOAJ |
| description | In this paper, a novel low voltage low power current buffer was presented. The proposed structure was implemented in CMOS technology and is the second generation of OCB (orderly current buffer) called OCBII. This generation is arranged in single input-single output configuration and has modular structure. It is theoretically analyzed and the formulae of its most important parameters are derived. Pre and Post-layout plus Monte Carlo simulations were performed under ±0.75 V by Cadence using TSMC 0.18 µm CMOS technology parameters up to 3rd order. The proposed structure could expand and act as a dual output buffer in which the second output shows extremely high impedance because of its cascode configuration. The results prove that OCBII makes it possible to achieve very low values of input impedance under low supply voltages and low power dissipation. The most important parameters of 1st, 2nd and 3rd orders, i.e. input impedance (Rin), -3 dB bandwidth (BW), power dissipation (Pd) and output impedance (Ro) were found respectively in Pre-layout plus Monte Carlo results as:
1st order: Rin (52.4 Ω), BW (733.7 MHz), Pd (225.6 µW), Ro (105.6 kΩ)
2nd order: Rin (3.8 Ω), BW (576.4 MHz), Pd (307 µW), Ro (106.4 kΩ)
3rd order: Rin (0.34 Ω), BW (566.9 MHz), Pd (535.6 µW), Ro (118.2 kΩ)
And in Post-layout plus Monte Carlo results as:
1st order: Rin (59.9 Ω), BW (609.6 MHz), Pd (212.4 µW), Ro (106.9 kΩ)
2nd order: Rin (11.3 Ω), BW (529.3 MHz), Pd (389.9 µW), Ro (109.8 kΩ)
3rd order: Rin (5.8 Ω), BW (526.5 MHz), Pd (514.5 µW), Ro (125.5 kΩ)
Corner cases simulation results are also provided indicating well PVT insensitivity advantage of the block. |
| first_indexed | 2024-12-14T23:25:30Z |
| format | Article |
| id | doaj.art-4aa8ed39c8c44ec3be38b458fbd5a9d7 |
| institution | Directory Open Access Journal |
| issn | 1735-2827 2383-3890 |
| language | English |
| last_indexed | 2024-12-14T23:25:30Z |
| publishDate | 2019-06-01 |
| publisher | Iran University of Science and Technology |
| record_format | Article |
| series | Iranian Journal of Electrical and Electronic Engineering |
| spelling | doaj.art-4aa8ed39c8c44ec3be38b458fbd5a9d72022-12-21T22:43:48ZengIran University of Science and TechnologyIranian Journal of Electrical and Electronic Engineering1735-28272383-38902019-06-01152258268A Low Voltage Low Power CMOS Implementation of Second Generation Orderly Current BufferS. J. Azhari0M. Zareie1 Department of Electrical Engineering, Iran University of Science and Technology (IUST), Tehran, Iran. Department of Electrical Engineering, Iran University of Science and Technology (IUST), Tehran, Iran. In this paper, a novel low voltage low power current buffer was presented. The proposed structure was implemented in CMOS technology and is the second generation of OCB (orderly current buffer) called OCBII. This generation is arranged in single input-single output configuration and has modular structure. It is theoretically analyzed and the formulae of its most important parameters are derived. Pre and Post-layout plus Monte Carlo simulations were performed under ±0.75 V by Cadence using TSMC 0.18 µm CMOS technology parameters up to 3rd order. The proposed structure could expand and act as a dual output buffer in which the second output shows extremely high impedance because of its cascode configuration. The results prove that OCBII makes it possible to achieve very low values of input impedance under low supply voltages and low power dissipation. The most important parameters of 1st, 2nd and 3rd orders, i.e. input impedance (Rin), -3 dB bandwidth (BW), power dissipation (Pd) and output impedance (Ro) were found respectively in Pre-layout plus Monte Carlo results as: 1st order: Rin (52.4 Ω), BW (733.7 MHz), Pd (225.6 µW), Ro (105.6 kΩ) 2nd order: Rin (3.8 Ω), BW (576.4 MHz), Pd (307 µW), Ro (106.4 kΩ) 3rd order: Rin (0.34 Ω), BW (566.9 MHz), Pd (535.6 µW), Ro (118.2 kΩ) And in Post-layout plus Monte Carlo results as: 1st order: Rin (59.9 Ω), BW (609.6 MHz), Pd (212.4 µW), Ro (106.9 kΩ) 2nd order: Rin (11.3 Ω), BW (529.3 MHz), Pd (389.9 µW), Ro (109.8 kΩ) 3rd order: Rin (5.8 Ω), BW (526.5 MHz), Pd (514.5 µW), Ro (125.5 kΩ) Corner cases simulation results are also provided indicating well PVT insensitivity advantage of the block.http://ijeee.iust.ac.ir/browse.php?a_code=A-10-46-4&slc_lang=en&sid=1Second Generation OCBCurrent BufferExtremely Low Input ImpedanceVery Wide Bandwidth Current BufferCurrent Mode. |
| spellingShingle | S. J. Azhari M. Zareie A Low Voltage Low Power CMOS Implementation of Second Generation Orderly Current Buffer Iranian Journal of Electrical and Electronic Engineering Second Generation OCB Current Buffer Extremely Low Input Impedance Very Wide Bandwidth Current Buffer Current Mode. |
| title | A Low Voltage Low Power CMOS Implementation of Second Generation Orderly Current Buffer |
| title_full | A Low Voltage Low Power CMOS Implementation of Second Generation Orderly Current Buffer |
| title_fullStr | A Low Voltage Low Power CMOS Implementation of Second Generation Orderly Current Buffer |
| title_full_unstemmed | A Low Voltage Low Power CMOS Implementation of Second Generation Orderly Current Buffer |
| title_short | A Low Voltage Low Power CMOS Implementation of Second Generation Orderly Current Buffer |
| title_sort | low voltage low power cmos implementation of second generation orderly current buffer |
| topic | Second Generation OCB Current Buffer Extremely Low Input Impedance Very Wide Bandwidth Current Buffer Current Mode. |
| url | http://ijeee.iust.ac.ir/browse.php?a_code=A-10-46-4&slc_lang=en&sid=1 |
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