Hardware‐assisted remote attestation design for critical embedded systems
Abstract Remote attestation, as a challenge‐response protocol, enables a trusted entity, called verifier, to ask a potentially infected device, called prover, to provide integrity assurance about its internal state. Remote attestation is becoming increasingly vital for embedded systems that serve in...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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Hindawi-IET
2023-05-01
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| Series: | IET Information Security |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/ise2.12113 |
| _version_ | 1797420929534394368 |
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| author | Munir Geden Kasper Rasmussen |
| author_facet | Munir Geden Kasper Rasmussen |
| author_sort | Munir Geden |
| collection | DOAJ |
| description | Abstract Remote attestation, as a challenge‐response protocol, enables a trusted entity, called verifier, to ask a potentially infected device, called prover, to provide integrity assurance about its internal state. Remote attestation is becoming increasingly vital for embedded systems that serve in many critical domains, as part of health, military, transportation and industry services, but still lack the most security features available to high‐end systems. In most attestation techniques, the prover provides a cryptographic checksum of its static memory contents, that is, code segments, to the verifier when requested to demonstrate that the device is loaded with the right software. However, those measurements are subject to two limitations. First, they cannot guarantee that the prover has always had legitimate software in the memory prior to attestation. This is because occasional measurements, triggered by the verifier, still leave the device vulnerable to the compromise between two attestation windows as a time‐of‐check‐to‐time‐of‐use (TOCTOU) problem. Second, including dynamic memory regions in the checksum calculation is not helpful in practice, since the verifier typically does not know what those regions should contain or which checksums should be accepted as valid. Hence, many attack scenarios residing in those dynamic regions (e.g. stack) would also go unnoticed. To reveal attack scenarios exploiting the memory regions and time windows left unattested, we propose an attestation scheme that can continuously monitor both static and dynamic memory regions with better spatial and temporal attestation coverage. Our monitoring mechanism is designed to be performed in real time using a novel hardware security module (HSM) connected to the prover's system bus. The proposed HSM monitors not only the integrity of the code on the prover but also its execution by checking the compliance of the bits seen on the bus according to a runtime integrity model (RIM) of the prover's software. Therefore, our attestation scheme is capable of reporting scenarios that violate both the (static) code and (dynamic) runtime integrity since the deployment time. |
| first_indexed | 2024-03-09T07:09:14Z |
| format | Article |
| id | doaj.art-4adbafaa22974954aba55f131de8eecf |
| institution | Directory Open Access Journal |
| issn | 1751-8709 1751-8717 |
| language | English |
| last_indexed | 2024-03-09T07:09:14Z |
| publishDate | 2023-05-01 |
| publisher | Hindawi-IET |
| record_format | Article |
| series | IET Information Security |
| spelling | doaj.art-4adbafaa22974954aba55f131de8eecf2023-12-03T09:15:33ZengHindawi-IETIET Information Security1751-87091751-87172023-05-0117351853310.1049/ise2.12113Hardware‐assisted remote attestation design for critical embedded systemsMunir Geden0Kasper Rasmussen1Department of Computer Science University of Oxford Oxford UKDepartment of Computer Science University of Oxford Oxford UKAbstract Remote attestation, as a challenge‐response protocol, enables a trusted entity, called verifier, to ask a potentially infected device, called prover, to provide integrity assurance about its internal state. Remote attestation is becoming increasingly vital for embedded systems that serve in many critical domains, as part of health, military, transportation and industry services, but still lack the most security features available to high‐end systems. In most attestation techniques, the prover provides a cryptographic checksum of its static memory contents, that is, code segments, to the verifier when requested to demonstrate that the device is loaded with the right software. However, those measurements are subject to two limitations. First, they cannot guarantee that the prover has always had legitimate software in the memory prior to attestation. This is because occasional measurements, triggered by the verifier, still leave the device vulnerable to the compromise between two attestation windows as a time‐of‐check‐to‐time‐of‐use (TOCTOU) problem. Second, including dynamic memory regions in the checksum calculation is not helpful in practice, since the verifier typically does not know what those regions should contain or which checksums should be accepted as valid. Hence, many attack scenarios residing in those dynamic regions (e.g. stack) would also go unnoticed. To reveal attack scenarios exploiting the memory regions and time windows left unattested, we propose an attestation scheme that can continuously monitor both static and dynamic memory regions with better spatial and temporal attestation coverage. Our monitoring mechanism is designed to be performed in real time using a novel hardware security module (HSM) connected to the prover's system bus. The proposed HSM monitors not only the integrity of the code on the prover but also its execution by checking the compliance of the bits seen on the bus according to a runtime integrity model (RIM) of the prover's software. Therefore, our attestation scheme is capable of reporting scenarios that violate both the (static) code and (dynamic) runtime integrity since the deployment time.https://doi.org/10.1049/ise2.12113embedded systemsprotocolssecurity |
| spellingShingle | Munir Geden Kasper Rasmussen Hardware‐assisted remote attestation design for critical embedded systems IET Information Security embedded systems protocols security |
| title | Hardware‐assisted remote attestation design for critical embedded systems |
| title_full | Hardware‐assisted remote attestation design for critical embedded systems |
| title_fullStr | Hardware‐assisted remote attestation design for critical embedded systems |
| title_full_unstemmed | Hardware‐assisted remote attestation design for critical embedded systems |
| title_short | Hardware‐assisted remote attestation design for critical embedded systems |
| title_sort | hardware assisted remote attestation design for critical embedded systems |
| topic | embedded systems protocols security |
| url | https://doi.org/10.1049/ise2.12113 |
| work_keys_str_mv | AT munirgeden hardwareassistedremoteattestationdesignforcriticalembeddedsystems AT kasperrasmussen hardwareassistedremoteattestationdesignforcriticalembeddedsystems |