Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard
The rapid advancement of powerful quantum computers poses a significant security risk to current public-key cryptosystems, which heavily rely on the computational complexity of problems such as discrete logarithms and integer factorization. As a result, CRYSTALS-Dilithium, a lattice-based digital si...
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| Format: | Article |
| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10445248/ |
| _version_ | 1797277630471340032 |
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| author | Quang Dang Truong Phap Ngoc Duong Hanho Lee |
| author_facet | Quang Dang Truong Phap Ngoc Duong Hanho Lee |
| author_sort | Quang Dang Truong |
| collection | DOAJ |
| description | The rapid advancement of powerful quantum computers poses a significant security risk to current public-key cryptosystems, which heavily rely on the computational complexity of problems such as discrete logarithms and integer factorization. As a result, CRYSTALS-Dilithium, a lattice-based digital signature scheme with the potential to be an alternative algorithm that can withstand both quantum and classical attacks, has been standardized as ML-DSA after NIST Post-Quantum Cryptography competition. While prior studies have proposed hardware designs to accelerate this cryptosystem, there is room for further optimization in the tradeoff between performance and hardware consumption. This paper addresses these limitations by presenting an efficient low-latency hardware architecture for ML-DSA, leveraging optimized timing schedules for its three main algorithms. The hardware implementation enables runtime switching main operations in ML-DSA with various security levels. We design flexible arithmetic and hash modules tailored for ML-DSA, the most time-consuming submodules and key determinants of the scheme implementation. Combined with efficient operation scheduling to maximize the utilized time of submodules, our design achieves the best latency among FPGA-based implementations, outperforming state-of-the-art works by 1.27<inline-formula> <tex-math notation="LaTeX">$\sim 2.58\times $ </tex-math></inline-formula> in terms of the area-time tradeoff metric. Therefore, the proposed hardware architecture demonstrates its practical applicability for digital signature cryptosystems in post-quantum era. |
| first_indexed | 2024-03-07T15:52:10Z |
| format | Article |
| id | doaj.art-4d7bd2479db249c4a72a573e49140103 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-03-07T15:52:10Z |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-4d7bd2479db249c4a72a573e491401032024-03-05T00:00:16ZengIEEEIEEE Access2169-35362024-01-0112323953240710.1109/ACCESS.2024.337047010445248Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature StandardQuang Dang Truong0https://orcid.org/0009-0003-9350-168XPhap Ngoc Duong1https://orcid.org/0000-0002-0311-9387Hanho Lee2https://orcid.org/0000-0001-8815-1927Department of Electrical and Computer Engineering, Inha University, Incheon, South KoreaDepartment of Electrical and Computer Engineering, Inha University, Incheon, South KoreaDepartment of Electrical and Computer Engineering, Inha University, Incheon, South KoreaThe rapid advancement of powerful quantum computers poses a significant security risk to current public-key cryptosystems, which heavily rely on the computational complexity of problems such as discrete logarithms and integer factorization. As a result, CRYSTALS-Dilithium, a lattice-based digital signature scheme with the potential to be an alternative algorithm that can withstand both quantum and classical attacks, has been standardized as ML-DSA after NIST Post-Quantum Cryptography competition. While prior studies have proposed hardware designs to accelerate this cryptosystem, there is room for further optimization in the tradeoff between performance and hardware consumption. This paper addresses these limitations by presenting an efficient low-latency hardware architecture for ML-DSA, leveraging optimized timing schedules for its three main algorithms. The hardware implementation enables runtime switching main operations in ML-DSA with various security levels. We design flexible arithmetic and hash modules tailored for ML-DSA, the most time-consuming submodules and key determinants of the scheme implementation. Combined with efficient operation scheduling to maximize the utilized time of submodules, our design achieves the best latency among FPGA-based implementations, outperforming state-of-the-art works by 1.27<inline-formula> <tex-math notation="LaTeX">$\sim 2.58\times $ </tex-math></inline-formula> in terms of the area-time tradeoff metric. Therefore, the proposed hardware architecture demonstrates its practical applicability for digital signature cryptosystems in post-quantum era.https://ieeexplore.ieee.org/document/10445248/Post-quantum cryptography (PQC)module-lattice-based digital signature standard (ML-DSA)crystals-Dilithiumlattice-based cryptography (LBC)number theoretic transform (NTT) |
| spellingShingle | Quang Dang Truong Phap Ngoc Duong Hanho Lee Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard IEEE Access Post-quantum cryptography (PQC) module-lattice-based digital signature standard (ML-DSA) crystals-Dilithium lattice-based cryptography (LBC) number theoretic transform (NTT) |
| title | Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard |
| title_full | Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard |
| title_fullStr | Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard |
| title_full_unstemmed | Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard |
| title_short | Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard |
| title_sort | efficient low latency hardware architecture for module lattice based digital signature standard |
| topic | Post-quantum cryptography (PQC) module-lattice-based digital signature standard (ML-DSA) crystals-Dilithium lattice-based cryptography (LBC) number theoretic transform (NTT) |
| url | https://ieeexplore.ieee.org/document/10445248/ |
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