Design of Multi-bit Pulsed Latches with Scan Input in CMOS ONK65 Technology
This paper presents a new multi-bit pulse latch design that places innovative emphasis on the integration of scan input for automatic test pattern generation (ATPG). Two different designs have been developed in ONK65 technology (65 nm process): the first with standard threshold voltage (SVT) tailore...
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| Format: | Article |
| Language: | English |
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Spolecnost pro radioelektronicke inzenyrstvi
2023-12-01
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| Series: | Radioengineering |
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| Online Access: | https://www.radioeng.cz/fulltexts/2023/23_04_0557_0567.pdf |