RTL-DEVS: HDL Design and Simulation Methodology for DEVS Formalism-Based Simulation Tool
DEVS (Discrete Event System Specification) is widely used in modeling and simulation fields to design, validate, and implement complex response systems. DEVS provides a robust formalism for system design using event-driven, state-based models with explicitly defined temporal information. We extend t...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-12-01
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| Series: | Telecom |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2673-4001/4/1/2 |
| _version_ | 1797608833828257792 |
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| author | Bo-Seung Kwon Sang-Won Jung Young-Dan Noh Jong-Sik Lee Young-Shin Han |
| author_facet | Bo-Seung Kwon Sang-Won Jung Young-Dan Noh Jong-Sik Lee Young-Shin Han |
| author_sort | Bo-Seung Kwon |
| collection | DOAJ |
| description | DEVS (Discrete Event System Specification) is widely used in modeling and simulation fields to design, validate, and implement complex response systems. DEVS provides a robust formalism for system design using event-driven, state-based models with explicitly defined temporal information. We extend the RTL-DEVS model based on DEVS formalism to enable part of Verilog simulation in DEVS-based simulation tools. The simulation based on RTL-DEVS methodology, which imitates Verilog’s testbench and behavioral module, confirmed through experiments that RTL simulation can be performed sufficiently through the code elaboration process. In multiple simulation results, Verilog simulation and RTL-DEVS-based simulation were able to output equivalent results under limited conditions. DEVS formalism-based modeling can be extended to other DEVS-based simulators when using model-type exchange tools, and this means that the advanced functions or classes of RTL simulation tools can be applied using higher-level language tools. |
| first_indexed | 2024-03-11T05:49:11Z |
| format | Article |
| id | doaj.art-4fa08528fe04494b8cc7208d3a13a843 |
| institution | Directory Open Access Journal |
| issn | 2673-4001 |
| language | English |
| last_indexed | 2024-03-11T05:49:11Z |
| publishDate | 2022-12-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Telecom |
| spelling | doaj.art-4fa08528fe04494b8cc7208d3a13a8432023-11-17T14:11:46ZengMDPI AGTelecom2673-40012022-12-0141153010.3390/telecom4010002RTL-DEVS: HDL Design and Simulation Methodology for DEVS Formalism-Based Simulation ToolBo-Seung Kwon0Sang-Won Jung1Young-Dan Noh2Jong-Sik Lee3Young-Shin Han4Department of Computer Engineering, Inha University, 100 Inha-ro, Michuhol-gu, Incheon 22212, Republic of KoreaDepartment of Computer Engineering, Inha University, 100 Inha-ro, Michuhol-gu, Incheon 22212, Republic of KoreaDepartment of Computer Engineering, Inha University, 100 Inha-ro, Michuhol-gu, Incheon 22212, Republic of KoreaDepartment of Computer Engineering, Inha University, 100 Inha-ro, Michuhol-gu, Incheon 22212, Republic of KoreaFrontier College, Inha University, 100 Inha-ro, Michuhol-gu, Incheon 22212, Republic of KoreaDEVS (Discrete Event System Specification) is widely used in modeling and simulation fields to design, validate, and implement complex response systems. DEVS provides a robust formalism for system design using event-driven, state-based models with explicitly defined temporal information. We extend the RTL-DEVS model based on DEVS formalism to enable part of Verilog simulation in DEVS-based simulation tools. The simulation based on RTL-DEVS methodology, which imitates Verilog’s testbench and behavioral module, confirmed through experiments that RTL simulation can be performed sufficiently through the code elaboration process. In multiple simulation results, Verilog simulation and RTL-DEVS-based simulation were able to output equivalent results under limited conditions. DEVS formalism-based modeling can be extended to other DEVS-based simulators when using model-type exchange tools, and this means that the advanced functions or classes of RTL simulation tools can be applied using higher-level language tools.https://www.mdpi.com/2673-4001/4/1/2modelsimulationHDLhardware description languageRTL |
| spellingShingle | Bo-Seung Kwon Sang-Won Jung Young-Dan Noh Jong-Sik Lee Young-Shin Han RTL-DEVS: HDL Design and Simulation Methodology for DEVS Formalism-Based Simulation Tool Telecom model simulation HDL hardware description language RTL |
| title | RTL-DEVS: HDL Design and Simulation Methodology for DEVS Formalism-Based Simulation Tool |
| title_full | RTL-DEVS: HDL Design and Simulation Methodology for DEVS Formalism-Based Simulation Tool |
| title_fullStr | RTL-DEVS: HDL Design and Simulation Methodology for DEVS Formalism-Based Simulation Tool |
| title_full_unstemmed | RTL-DEVS: HDL Design and Simulation Methodology for DEVS Formalism-Based Simulation Tool |
| title_short | RTL-DEVS: HDL Design and Simulation Methodology for DEVS Formalism-Based Simulation Tool |
| title_sort | rtl devs hdl design and simulation methodology for devs formalism based simulation tool |
| topic | model simulation HDL hardware description language RTL |
| url | https://www.mdpi.com/2673-4001/4/1/2 |
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