An LDPC Encoder Architecture With Up to 47.5 Gbps Throughput for DVB-S2/S2X Standards
Low-Density Parity-Check (LDPC) code is a type of forward error-correction code with excellent performance, and has been widely used in many modern communication standards. The second-generation satellite broadcasting standard (DVB-S2) and its extension (DVB-S2X) adopt a special Irregular Repeated A...
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| Format: | Article |
| Language: | English |
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IEEE
2022-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/9712323/ |
| _version_ | 1797837364687536128 |
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| author | Decai Liu Yanfei Luo Yunfeng Li Zhijie Wang Zhengxuan Li Qianwu Zhang Junjie Zhang Yingchun Li |
| author_facet | Decai Liu Yanfei Luo Yunfeng Li Zhijie Wang Zhengxuan Li Qianwu Zhang Junjie Zhang Yingchun Li |
| author_sort | Decai Liu |
| collection | DOAJ |
| description | Low-Density Parity-Check (LDPC) code is a type of forward error-correction code with excellent performance, and has been widely used in many modern communication standards. The second-generation satellite broadcasting standard (DVB-S2) and its extension (DVB-S2X) adopt a special Irregular Repeated Accumulate (IRA) LDPC code as inner coding scheme. However, due to the large block size, most of the architectures proposed so far use Random Access Memory (RAM) to store and update the encoding results, and the delay caused by address-controlled read and write operations and barrel shift during computation inevitably limits the upper bound of encoder throughput. In this paper, by extracting the periodicity of the parity-check matrix, we introduce a fast encoding algorithm that can efficiently process the multiplication of the information sequence and a large-dimensional sparse matrix, and propose an encoder architecture with low encoding delay and high throughput. The proposed architecture has been implemented and tested on a Xilinx Kintex-7 FPGA, and the result show that the encoder architecture can achieve the highest throughput of 47.5 Gbps at a clock frequency of 280 MHz. |
| first_indexed | 2024-04-09T15:24:42Z |
| format | Article |
| id | doaj.art-506b37942e2248e995d0c66e996f70db |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-04-09T15:24:42Z |
| publishDate | 2022-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-506b37942e2248e995d0c66e996f70db2023-04-28T23:00:24ZengIEEEIEEE Access2169-35362022-01-0110190221903210.1109/ACCESS.2022.31510869712323An LDPC Encoder Architecture With Up to 47.5 Gbps Throughput for DVB-S2/S2X StandardsDecai Liu0https://orcid.org/0000-0001-5776-0519Yanfei Luo1https://orcid.org/0000-0002-1973-2784Yunfeng Li2https://orcid.org/0000-0003-3709-0188Zhijie Wang3https://orcid.org/0000-0002-4545-4642Zhengxuan Li4https://orcid.org/0000-0001-9907-1543Qianwu Zhang5https://orcid.org/0000-0001-8614-5267Junjie Zhang6https://orcid.org/0000-0002-9258-1177Yingchun Li7https://orcid.org/0000-0001-6914-7578Key Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai, ChinaKey Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai, ChinaKey Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai, ChinaKey Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai, ChinaKey Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai, ChinaKey Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai, ChinaKey Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai, ChinaKey Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai, ChinaLow-Density Parity-Check (LDPC) code is a type of forward error-correction code with excellent performance, and has been widely used in many modern communication standards. The second-generation satellite broadcasting standard (DVB-S2) and its extension (DVB-S2X) adopt a special Irregular Repeated Accumulate (IRA) LDPC code as inner coding scheme. However, due to the large block size, most of the architectures proposed so far use Random Access Memory (RAM) to store and update the encoding results, and the delay caused by address-controlled read and write operations and barrel shift during computation inevitably limits the upper bound of encoder throughput. In this paper, by extracting the periodicity of the parity-check matrix, we introduce a fast encoding algorithm that can efficiently process the multiplication of the information sequence and a large-dimensional sparse matrix, and propose an encoder architecture with low encoding delay and high throughput. The proposed architecture has been implemented and tested on a Xilinx Kintex-7 FPGA, and the result show that the encoder architecture can achieve the highest throughput of 47.5 Gbps at a clock frequency of 280 MHz.https://ieeexplore.ieee.org/document/9712323/Low-density parity-check codeDVB-S2/S2Xencoder architecturehigh throughputFPGA |
| spellingShingle | Decai Liu Yanfei Luo Yunfeng Li Zhijie Wang Zhengxuan Li Qianwu Zhang Junjie Zhang Yingchun Li An LDPC Encoder Architecture With Up to 47.5 Gbps Throughput for DVB-S2/S2X Standards IEEE Access Low-density parity-check code DVB-S2/S2X encoder architecture high throughput FPGA |
| title | An LDPC Encoder Architecture With Up to 47.5 Gbps Throughput for DVB-S2/S2X Standards |
| title_full | An LDPC Encoder Architecture With Up to 47.5 Gbps Throughput for DVB-S2/S2X Standards |
| title_fullStr | An LDPC Encoder Architecture With Up to 47.5 Gbps Throughput for DVB-S2/S2X Standards |
| title_full_unstemmed | An LDPC Encoder Architecture With Up to 47.5 Gbps Throughput for DVB-S2/S2X Standards |
| title_short | An LDPC Encoder Architecture With Up to 47.5 Gbps Throughput for DVB-S2/S2X Standards |
| title_sort | ldpc encoder architecture with up to 47 5 gbps throughput for dvb s2 s2x standards |
| topic | Low-density parity-check code DVB-S2/S2X encoder architecture high throughput FPGA |
| url | https://ieeexplore.ieee.org/document/9712323/ |
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