An Ultra-Area-Efficient 1024-Point In-Memory FFT Processor
Current computation architectures rely on more processor-centric design principles. On the other hand, the inevitable increase in the amount of data that applications need forces researchers to design novel processor architectures that are more data-centric. By following this principle, this study p...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2019-07-01
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| Series: | Micromachines |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2072-666X/10/8/509 |
| Summary: | Current computation architectures rely on more processor-centric design principles. On the other hand, the inevitable increase in the amount of data that applications need forces researchers to design novel processor architectures that are more data-centric. By following this principle, this study proposes an area-efficient Fast Fourier Transform (FFT) processor through in-memory computing. The proposed architecture occupies the smallest footprint of around 0.1 <inline-formula><math display="inline"><semantics><msup><mi>mm</mi><mn>2</mn></msup></semantics></math></inline-formula> inside its class together with acceptable power efficiency. According to the results, the processor exhibits the highest area efficiency (<inline-formula><math display="inline"><semantics><mrow><mi>FFT</mi><mo>/</mo><mi mathvariant="normal">s</mi><mo>/</mo><mi>area</mi></mrow></semantics></math></inline-formula>) among the existing FFT processors in the current literature. |
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| ISSN: | 2072-666X |