FPGA-Based Architecture for Medium Access Techniques in Broadband PLC
In this paper, two real-time architectures of medium access techniques useful for future generation of wireline and wireless communication systems are presented. One architecture is based on discrete cosine transform (DCT), while the second approach implements a filter-bank multi-carrier (FBMC) syst...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2018-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/8300308/ |
| _version_ | 1818644546418900992 |
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| author | Pablo Poudereux Alvaro Hernandez Fernando Cruz-Roldan Raul Mateos |
| author_facet | Pablo Poudereux Alvaro Hernandez Fernando Cruz-Roldan Raul Mateos |
| author_sort | Pablo Poudereux |
| collection | DOAJ |
| description | In this paper, two real-time architectures of medium access techniques useful for future generation of wireline and wireless communication systems are presented. One architecture is based on discrete cosine transform (DCT), while the second approach implements a filter-bank multi-carrier (FBMC) system. A comparative analysis, in terms of resource consumption, performance, and precision, is shown. The comparison considers a floating-point model, a fixed-point model, and experimental tests. These models make it possible to evaluate the effect of the fixed-point precision in the implementation and, in turn, to verify the correctness of the developed architecture. The simulation models and the experimental tests have been carried out in different practical environments in order to achieve a further analysis. The two proposed architectures have been implemented on a field-programmable gate array (FPGA) device. Furthermore, the architectures have been included as advanced peripherals in a system-on-chip, which also integrates a soft microprocessor to monitor the whole system and manage the data transfers. As a communication scenario, the proposed architectures have been particularized to operate in real time while meeting all timing requirements defined by a broadband power line communications standard. For that case, the system has achieved a desired transmission rate of 62.5 Ms/s at the converters, providing mean squared errors, at the output for an ideal channel, below 3·10<sup>-5</sup> for both the DCT and FBMC approaches, whereas each transmitter/receiver requires around 50% of the DSP cells available in the Xilinx XC6VLX240T FPGA, the most demanded resource in the device. |
| first_indexed | 2024-12-17T00:16:34Z |
| format | Article |
| id | doaj.art-535c79a899e64c28b5975c6ab116ed5e |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-17T00:16:34Z |
| publishDate | 2018-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-535c79a899e64c28b5975c6ab116ed5e2022-12-21T22:10:42ZengIEEEIEEE Access2169-35362018-01-0169534954210.1109/ACCESS.2018.28083718300308FPGA-Based Architecture for Medium Access Techniques in Broadband PLCPablo Poudereux0Alvaro Hernandez1https://orcid.org/0000-0001-9308-8133Fernando Cruz-Roldan2https://orcid.org/0000-0001-6843-5199Raul Mateos3Electronics Department, Universidad de Alcalá, Alcalá de Henares, SpainElectronics Department, Universidad de Alcalá, Alcalá de Henares, SpainSignal Theory and Communications Department, Universidad de Alcalá, Alcalá de Henares, SpainElectronics Department, Universidad de Alcalá, Alcalá de Henares, SpainIn this paper, two real-time architectures of medium access techniques useful for future generation of wireline and wireless communication systems are presented. One architecture is based on discrete cosine transform (DCT), while the second approach implements a filter-bank multi-carrier (FBMC) system. A comparative analysis, in terms of resource consumption, performance, and precision, is shown. The comparison considers a floating-point model, a fixed-point model, and experimental tests. These models make it possible to evaluate the effect of the fixed-point precision in the implementation and, in turn, to verify the correctness of the developed architecture. The simulation models and the experimental tests have been carried out in different practical environments in order to achieve a further analysis. The two proposed architectures have been implemented on a field-programmable gate array (FPGA) device. Furthermore, the architectures have been included as advanced peripherals in a system-on-chip, which also integrates a soft microprocessor to monitor the whole system and manage the data transfers. As a communication scenario, the proposed architectures have been particularized to operate in real time while meeting all timing requirements defined by a broadband power line communications standard. For that case, the system has achieved a desired transmission rate of 62.5 Ms/s at the converters, providing mean squared errors, at the output for an ideal channel, below 3·10<sup>-5</sup> for both the DCT and FBMC approaches, whereas each transmitter/receiver requires around 50% of the DSP cells available in the Xilinx XC6VLX240T FPGA, the most demanded resource in the device.https://ieeexplore.ieee.org/document/8300308/Field-programmable gate arraysmulti-carrier communication (MCM)filter-bank multi-carrier (FBMC) systemsbroadband power-line communicationsdiscrete cosine transform (DCT) |
| spellingShingle | Pablo Poudereux Alvaro Hernandez Fernando Cruz-Roldan Raul Mateos FPGA-Based Architecture for Medium Access Techniques in Broadband PLC IEEE Access Field-programmable gate arrays multi-carrier communication (MCM) filter-bank multi-carrier (FBMC) systems broadband power-line communications discrete cosine transform (DCT) |
| title | FPGA-Based Architecture for Medium Access Techniques in Broadband PLC |
| title_full | FPGA-Based Architecture for Medium Access Techniques in Broadband PLC |
| title_fullStr | FPGA-Based Architecture for Medium Access Techniques in Broadband PLC |
| title_full_unstemmed | FPGA-Based Architecture for Medium Access Techniques in Broadband PLC |
| title_short | FPGA-Based Architecture for Medium Access Techniques in Broadband PLC |
| title_sort | fpga based architecture for medium access techniques in broadband plc |
| topic | Field-programmable gate arrays multi-carrier communication (MCM) filter-bank multi-carrier (FBMC) systems broadband power-line communications discrete cosine transform (DCT) |
| url | https://ieeexplore.ieee.org/document/8300308/ |
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