From SW Timing Analysis and Safety Logging to HW Implementation: A Possible Solution with an Integrated and Low-Power Logger Approach
In this manuscript, we propose a configurable hardware device in order to build a coherent data log unit. We address the need for analyzing mixed-criticality systems, thus guaranteeing the best performances without introducing additional sources of interference. Log data are essential to inspect the...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2023-11-01
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| Series: | Journal of Low Power Electronics and Applications |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2079-9268/13/4/59 |
| _version_ | 1827574481010294784 |
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| author | Francesco Cosimi Antonio Arena Paolo Gai Sergio Saponara |
| author_facet | Francesco Cosimi Antonio Arena Paolo Gai Sergio Saponara |
| author_sort | Francesco Cosimi |
| collection | DOAJ |
| description | In this manuscript, we propose a configurable hardware device in order to build a coherent data log unit. We address the need for analyzing mixed-criticality systems, thus guaranteeing the best performances without introducing additional sources of interference. Log data are essential to inspect the behavior of running applications when safety analyses or worst-case execution time measurements are performed. Furthermore, performance and timing investigations are useful for solving scheduling issues to balance resource budgets and investigate misbehavior and failure causes. We additionally present a performance evaluation and log capabilities by means of simulations on a RISC-V use case. The simulations highlight that such a data log unit can trace the execution from a single- to an octa-core microcontroller. Such an analysis allows a silicon developer to obtain the right sizings and timings of devices during the development phase. Finally, we present an analysis of a real RISC-V implementation for a Xilinx UltraScale+ FPGA, which was obtained with Vivado 2018. The results show that our data log unit implementation does not introduce a significant area overhead if compared to the RISC-V core targeted for tests, and that the timing constraints are not violated. |
| first_indexed | 2024-03-08T20:37:45Z |
| format | Article |
| id | doaj.art-5468c79cf3064450ab949f59c7413fee |
| institution | Directory Open Access Journal |
| issn | 2079-9268 |
| language | English |
| last_indexed | 2024-03-08T20:37:45Z |
| publishDate | 2023-11-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Journal of Low Power Electronics and Applications |
| spelling | doaj.art-5468c79cf3064450ab949f59c7413fee2023-12-22T14:18:19ZengMDPI AGJournal of Low Power Electronics and Applications2079-92682023-11-011345910.3390/jlpea13040059From SW Timing Analysis and Safety Logging to HW Implementation: A Possible Solution with an Integrated and Low-Power Logger ApproachFrancesco Cosimi0Antonio Arena1Paolo Gai2Sergio Saponara3Department of Information Engineering, University of Pisa, 56122 Pisa, ItalyHuawei Pisa Research Center, 56121 Pisa, ItalyHuawei Pisa Research Center, 56121 Pisa, ItalyDepartment of Information Engineering, University of Pisa, 56122 Pisa, ItalyIn this manuscript, we propose a configurable hardware device in order to build a coherent data log unit. We address the need for analyzing mixed-criticality systems, thus guaranteeing the best performances without introducing additional sources of interference. Log data are essential to inspect the behavior of running applications when safety analyses or worst-case execution time measurements are performed. Furthermore, performance and timing investigations are useful for solving scheduling issues to balance resource budgets and investigate misbehavior and failure causes. We additionally present a performance evaluation and log capabilities by means of simulations on a RISC-V use case. The simulations highlight that such a data log unit can trace the execution from a single- to an octa-core microcontroller. Such an analysis allows a silicon developer to obtain the right sizings and timings of devices during the development phase. Finally, we present an analysis of a real RISC-V implementation for a Xilinx UltraScale+ FPGA, which was obtained with Vivado 2018. The results show that our data log unit implementation does not introduce a significant area overhead if compared to the RISC-V core targeted for tests, and that the timing constraints are not violated.https://www.mdpi.com/2079-9268/13/4/59automotivedata logexecution tracinghardwareRISC-Vsafety |
| spellingShingle | Francesco Cosimi Antonio Arena Paolo Gai Sergio Saponara From SW Timing Analysis and Safety Logging to HW Implementation: A Possible Solution with an Integrated and Low-Power Logger Approach Journal of Low Power Electronics and Applications automotive data log execution tracing hardware RISC-V safety |
| title | From SW Timing Analysis and Safety Logging to HW Implementation: A Possible Solution with an Integrated and Low-Power Logger Approach |
| title_full | From SW Timing Analysis and Safety Logging to HW Implementation: A Possible Solution with an Integrated and Low-Power Logger Approach |
| title_fullStr | From SW Timing Analysis and Safety Logging to HW Implementation: A Possible Solution with an Integrated and Low-Power Logger Approach |
| title_full_unstemmed | From SW Timing Analysis and Safety Logging to HW Implementation: A Possible Solution with an Integrated and Low-Power Logger Approach |
| title_short | From SW Timing Analysis and Safety Logging to HW Implementation: A Possible Solution with an Integrated and Low-Power Logger Approach |
| title_sort | from sw timing analysis and safety logging to hw implementation a possible solution with an integrated and low power logger approach |
| topic | automotive data log execution tracing hardware RISC-V safety |
| url | https://www.mdpi.com/2079-9268/13/4/59 |
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