Economical interpolator in a ΣΔ D/A converter
The place of interpolator in ΣΔ DACs was briefly discussed. The summarized structure of the most common interpolators was provided. The more applicable interpolators’ structures were suggested and analyzed in comparison with similar one. Having changed the structure of incomplete interpolator and ha...
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| Format: | Article |
| Language: | English |
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Vilnius Gediminas Technical University
2010-02-01
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| Series: | Mokslas: Lietuvos Ateitis |
| Subjects: | |
| Online Access: | http://journals.vgtu.lt/index.php/MLA/article/view/10060 |
| _version_ | 1818559006267932672 |
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| author | Vytenis Puidokas |
| author_facet | Vytenis Puidokas |
| author_sort | Vytenis Puidokas |
| collection | DOAJ |
| description | The place of interpolator in ΣΔ DACs was briefly discussed. The summarized structure of the most common interpolators was provided. The more applicable interpolators’ structures were suggested and analyzed in comparison with similar one. Having changed the structure of incomplete interpolator and having optimized the stages, it was possible to improve the characteristic of amplitude transfer by 17 dB with less non-zero coefficients and much less FPGA resources. After experimental research of the full converter system (interpolator, modulator and output filter) it was defined that the designed interpolator (including 17 dB gaining) suits only a very limited set of modulators. Another version of interpolator was offered for the system, ensuring the suppression of the additional frequency band in the whole system above 99 dB instead of the previous 66 dB (or 49 dB in the similar version of interpolator).
Article in Lithuanian
Ekonomiškas interpoliatorius Σ∆ SA keitiklyje
Santrauka
Trumpai aptarta interpoliatoriaus vieta Σ∆ skaičius analogas keitikliuose. Pateikta apibendrinta interpoliatoriaus struktūrinė schema. Pasiūlytos ir išanalizuotos tinkamesnės interpoliatorių struktūros lyginant su analogu. Pakeitus nepilnojo interpoliatoriaus struktūrą ir optimizavus pakopas, sugebėta su mažiau nenulinių koeficientų ir gerokai mažiau LPL matricos resursų amplitudės perdavimo charakteristiką pagerinti net 17 dB. Pilnos keitiklio sistemos (interpoliatoriaus, moduliatorius, išėjimo filtras) eksperimentinis tyrimas parodė, jog suprojektuotas interpoliatorius (įskaitant 17 dB laimėjimą) tinka tik ribotam moduliatorių ratui. Sistemai pasiūlytas dar vienas – trijų pakopų interpoliatoriaus variantas, užtikrinantis visos sistemos pašalinės dažnių juostos slopinimą virš 99 dB vietoj buvusių 66 dB (arba 49 dB atraminiame variante).
Reikšminiai žodžiai: interpoliatorius, sigma, delta, SAK, LPL matrica. |
| first_indexed | 2024-12-14T00:19:44Z |
| format | Article |
| id | doaj.art-5582fb2468d6449badedcebc8eb57f2a |
| institution | Directory Open Access Journal |
| issn | 2029-2341 2029-2252 |
| language | English |
| last_indexed | 2024-12-14T00:19:44Z |
| publishDate | 2010-02-01 |
| publisher | Vilnius Gediminas Technical University |
| record_format | Article |
| series | Mokslas: Lietuvos Ateitis |
| spelling | doaj.art-5582fb2468d6449badedcebc8eb57f2a2022-12-21T23:25:16ZengVilnius Gediminas Technical UniversityMokslas: Lietuvos Ateitis2029-23412029-22522010-02-012110.3846/mla.2010.00784Economical interpolator in a ΣΔ D/A converterVytenis Puidokas0Vilniaus Gedimino technikos universitetas, LithuaniaThe place of interpolator in ΣΔ DACs was briefly discussed. The summarized structure of the most common interpolators was provided. The more applicable interpolators’ structures were suggested and analyzed in comparison with similar one. Having changed the structure of incomplete interpolator and having optimized the stages, it was possible to improve the characteristic of amplitude transfer by 17 dB with less non-zero coefficients and much less FPGA resources. After experimental research of the full converter system (interpolator, modulator and output filter) it was defined that the designed interpolator (including 17 dB gaining) suits only a very limited set of modulators. Another version of interpolator was offered for the system, ensuring the suppression of the additional frequency band in the whole system above 99 dB instead of the previous 66 dB (or 49 dB in the similar version of interpolator). Article in Lithuanian Ekonomiškas interpoliatorius Σ∆ SA keitiklyje Santrauka Trumpai aptarta interpoliatoriaus vieta Σ∆ skaičius analogas keitikliuose. Pateikta apibendrinta interpoliatoriaus struktūrinė schema. Pasiūlytos ir išanalizuotos tinkamesnės interpoliatorių struktūros lyginant su analogu. Pakeitus nepilnojo interpoliatoriaus struktūrą ir optimizavus pakopas, sugebėta su mažiau nenulinių koeficientų ir gerokai mažiau LPL matricos resursų amplitudės perdavimo charakteristiką pagerinti net 17 dB. Pilnos keitiklio sistemos (interpoliatoriaus, moduliatorius, išėjimo filtras) eksperimentinis tyrimas parodė, jog suprojektuotas interpoliatorius (įskaitant 17 dB laimėjimą) tinka tik ribotam moduliatorių ratui. Sistemai pasiūlytas dar vienas – trijų pakopų interpoliatoriaus variantas, užtikrinantis visos sistemos pašalinės dažnių juostos slopinimą virš 99 dB vietoj buvusių 66 dB (arba 49 dB atraminiame variante). Reikšminiai žodžiai: interpoliatorius, sigma, delta, SAK, LPL matrica.http://journals.vgtu.lt/index.php/MLA/article/view/10060interpolatorsigmadeltaDACFPGA |
| spellingShingle | Vytenis Puidokas Economical interpolator in a ΣΔ D/A converter Mokslas: Lietuvos Ateitis interpolator sigma delta DAC FPGA |
| title | Economical interpolator in a ΣΔ D/A converter |
| title_full | Economical interpolator in a ΣΔ D/A converter |
| title_fullStr | Economical interpolator in a ΣΔ D/A converter |
| title_full_unstemmed | Economical interpolator in a ΣΔ D/A converter |
| title_short | Economical interpolator in a ΣΔ D/A converter |
| title_sort | economical interpolator in a σδ d a converter |
| topic | interpolator sigma delta DAC FPGA |
| url | http://journals.vgtu.lt/index.php/MLA/article/view/10060 |
| work_keys_str_mv | AT vytenispuidokas economicalinterpolatorinasddaconverter |