A New Three-Phase Multi-Level Asymmetrical Inverter With Optimum Hardware Components
In this article, a novel three-phase asymmetrical multilevel inverter is presented. The proposed inverter is designed with an optimal hardware components to generate three-phase nineteen output voltage levels. The proposed inverter exhibits various advantages like a suitable output voltage waveform...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2020-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/9269325/ |
| _version_ | 1818591152126820352 |
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| author | C. Dhanamjayulu Palanisamy Kaliannan Sanjeevikumar Padmanaban Pandav Kiran Maroti Jens Bo Holm-Nielsen |
| author_facet | C. Dhanamjayulu Palanisamy Kaliannan Sanjeevikumar Padmanaban Pandav Kiran Maroti Jens Bo Holm-Nielsen |
| author_sort | C. Dhanamjayulu |
| collection | DOAJ |
| description | In this article, a novel three-phase asymmetrical multilevel inverter is presented. The proposed inverter is designed with an optimal hardware components to generate three-phase nineteen output voltage levels. The proposed inverter exhibits various advantages like a suitable output voltage waveform with improved power quality, lower total harmonic distortion (THD), and more moderate complexity, reduction in cost, reduced power losses, and improved efficiency. A comparison of the proposed topology in terms of several parameters with existing methods illustrates its merits and features. The proposed inverter tested with steady-state and dynamic load disturbances. Various experimental results are included in this article to validate the performance of the proposed inverter during various extremities. In addition, a detailed comparison is tabulated between simulation and experimental results graphically. The proposed inverter has been stable even during load disturbance conditions. The simulation and feasibility model are verified using a prototype model. |
| first_indexed | 2024-12-16T10:07:53Z |
| format | Article |
| id | doaj.art-56166e4829504292a502cb3434ceb1f5 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-16T10:07:53Z |
| publishDate | 2020-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-56166e4829504292a502cb3434ceb1f52022-12-21T22:35:37ZengIEEEIEEE Access2169-35362020-01-01821251521252810.1109/ACCESS.2020.30398319269325A New Three-Phase Multi-Level Asymmetrical Inverter With Optimum Hardware ComponentsC. Dhanamjayulu0https://orcid.org/0000-0003-0054-0149Palanisamy Kaliannan1https://orcid.org/0000-0003-4426-6292Sanjeevikumar Padmanaban2https://orcid.org/0000-0003-3212-2750Pandav Kiran Maroti3https://orcid.org/0000-0002-2516-9502Jens Bo Holm-Nielsen4https://orcid.org/0000-0002-0797-9691School of Electrical Engineering, Vellore Institute of Technology, Vellore, IndiaSchool of Electrical Engineering, Vellore Institute of Technology, Vellore, IndiaDepartment of Energy Technology, Aalborg University, Esbjerg, DenmarkDepartment of Energy Technology, Aalborg University, Esbjerg, DenmarkDepartment of Energy Technology, Aalborg University, Esbjerg, DenmarkIn this article, a novel three-phase asymmetrical multilevel inverter is presented. The proposed inverter is designed with an optimal hardware components to generate three-phase nineteen output voltage levels. The proposed inverter exhibits various advantages like a suitable output voltage waveform with improved power quality, lower total harmonic distortion (THD), and more moderate complexity, reduction in cost, reduced power losses, and improved efficiency. A comparison of the proposed topology in terms of several parameters with existing methods illustrates its merits and features. The proposed inverter tested with steady-state and dynamic load disturbances. Various experimental results are included in this article to validate the performance of the proposed inverter during various extremities. In addition, a detailed comparison is tabulated between simulation and experimental results graphically. The proposed inverter has been stable even during load disturbance conditions. The simulation and feasibility model are verified using a prototype model.https://ieeexplore.ieee.org/document/9269325/Multilevel inverter (MLI)total harmonic distortionasymmetrical multilevel inverter |
| spellingShingle | C. Dhanamjayulu Palanisamy Kaliannan Sanjeevikumar Padmanaban Pandav Kiran Maroti Jens Bo Holm-Nielsen A New Three-Phase Multi-Level Asymmetrical Inverter With Optimum Hardware Components IEEE Access Multilevel inverter (MLI) total harmonic distortion asymmetrical multilevel inverter |
| title | A New Three-Phase Multi-Level Asymmetrical Inverter With Optimum Hardware Components |
| title_full | A New Three-Phase Multi-Level Asymmetrical Inverter With Optimum Hardware Components |
| title_fullStr | A New Three-Phase Multi-Level Asymmetrical Inverter With Optimum Hardware Components |
| title_full_unstemmed | A New Three-Phase Multi-Level Asymmetrical Inverter With Optimum Hardware Components |
| title_short | A New Three-Phase Multi-Level Asymmetrical Inverter With Optimum Hardware Components |
| title_sort | new three phase multi level asymmetrical inverter with optimum hardware components |
| topic | Multilevel inverter (MLI) total harmonic distortion asymmetrical multilevel inverter |
| url | https://ieeexplore.ieee.org/document/9269325/ |
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