L0TP+: the Upgrade of the NA62 Level-0 Trigger Processor
The L0TP+ initiative is aimed at the upgrade of the FPGA-based Level-0 Trigger Processor (L0TP) of the NA62 experiment at CERN for the post-LS2 data taking, which is expected to happen at 100% of design beam intensity, corresponding to about 3.3 × 1012 protons per pulse on the beryllium target used...
| Main Authors: | , , , , , , , , , , , , , , |
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| Format: | Article |
| Language: | English |
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EDP Sciences
2020-01-01
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| Series: | EPJ Web of Conferences |
| Online Access: | https://www.epj-conferences.org/articles/epjconf/pdf/2020/21/epjconf_chep2020_01017.pdf |
| _version_ | 1819145254734921728 |
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| author | Ammendola Roberto Biagioni Andrea Ciardiello Andrea Cretaro Paolo Frezza Ottorino Lamanna Gianluca Lo Cicero Francesca Lonardo Alessandro Piandani Roberto Pontisso Luca Salamon Andrea Simula Francesco Soldi Dario Sozzi Marco Vicini Piero |
| author_facet | Ammendola Roberto Biagioni Andrea Ciardiello Andrea Cretaro Paolo Frezza Ottorino Lamanna Gianluca Lo Cicero Francesca Lonardo Alessandro Piandani Roberto Pontisso Luca Salamon Andrea Simula Francesco Soldi Dario Sozzi Marco Vicini Piero |
| author_sort | Ammendola Roberto |
| collection | DOAJ |
| description | The L0TP+ initiative is aimed at the upgrade of the FPGA-based Level-0 Trigger Processor (L0TP) of the NA62 experiment at CERN for the post-LS2 data taking, which is expected to happen at 100% of design beam intensity, corresponding to about 3.3 × 1012 protons per pulse on the beryllium target used to produce the kaons beam. Although tests performed at the end of 2018 showed a substantial robustness of the L0TP system also at full beam intensity, there are several reasons to motivate such an upgrade: i) avoid FPGA platform obsolescence, ii) make room for improvements in the firmware design leveraging a more capable FPGA device, iii) add new functionalities, iv) support the 4 beam intensity increase foreseen in future experiment upgrades. We singled out the Xilinx Virtex UltraScale+ VCU118 development board as the ideal platform for the project. L0TP+ seamless integration into the current NA62 TDAQ system and exact matching of L0TP functionalities represent the main requirements and focus of the project; nevertheless, the final design will include additional features, such as a PCIe RDMA engine to enable processing on CPU and GPU accelerators, and the partial reconfiguration of trigger firmware starting from a high level language description (C/C++). The latter capability is enabled by modern High Level Synthesis (HLS) tools, but to what extent this methodology can be applied to perform complex tasks in the L0 trigger, with its stringent latency requirements and the limits imposed by single FPGA resources, is currently being investigated. As a test case for this scenario we considered the online reconstruction of the RICH detector rings on an HLS generated module, using a dedicated primitives data stream with PM hits IDs. Besides, the chosen platform supports the Virtex Ultrascale+ FPGA wide I/O capabilities, allowing for straightforward integration of primitive streams from additional sub-detectors in order to improve the performance of the trigger. |
| first_indexed | 2024-12-22T12:55:07Z |
| format | Article |
| id | doaj.art-57d64d94f2c54952bdb6941c56657457 |
| institution | Directory Open Access Journal |
| issn | 2100-014X |
| language | English |
| last_indexed | 2024-12-22T12:55:07Z |
| publishDate | 2020-01-01 |
| publisher | EDP Sciences |
| record_format | Article |
| series | EPJ Web of Conferences |
| spelling | doaj.art-57d64d94f2c54952bdb6941c566574572022-12-21T18:25:07ZengEDP SciencesEPJ Web of Conferences2100-014X2020-01-012450101710.1051/epjconf/202024501017epjconf_chep2020_01017L0TP+: the Upgrade of the NA62 Level-0 Trigger ProcessorAmmendola Roberto0Biagioni Andrea1Ciardiello AndreaCretaro Paolo2Frezza Ottorino3Lamanna GianlucaLo Cicero Francesca4Lonardo Alessandro5Piandani Roberto6Pontisso Luca7Salamon Andrea8Simula Francesco9Soldi Dario10Sozzi MarcoVicini Piero11INFN, Sezione di Roma Tor VergataINFN, Sezione di RomaINFN, Sezione di RomaINFN, Sezione di RomaINFN, Sezione di RomaINFN, Sezione di RomaINFN, Sezione di PerugiaINFN, Sezione di RomaINFN, Sezione di Roma Tor VergataINFN, Sezione di RomaINFN, Sezione di TorinoINFN, Sezione di RomaThe L0TP+ initiative is aimed at the upgrade of the FPGA-based Level-0 Trigger Processor (L0TP) of the NA62 experiment at CERN for the post-LS2 data taking, which is expected to happen at 100% of design beam intensity, corresponding to about 3.3 × 1012 protons per pulse on the beryllium target used to produce the kaons beam. Although tests performed at the end of 2018 showed a substantial robustness of the L0TP system also at full beam intensity, there are several reasons to motivate such an upgrade: i) avoid FPGA platform obsolescence, ii) make room for improvements in the firmware design leveraging a more capable FPGA device, iii) add new functionalities, iv) support the 4 beam intensity increase foreseen in future experiment upgrades. We singled out the Xilinx Virtex UltraScale+ VCU118 development board as the ideal platform for the project. L0TP+ seamless integration into the current NA62 TDAQ system and exact matching of L0TP functionalities represent the main requirements and focus of the project; nevertheless, the final design will include additional features, such as a PCIe RDMA engine to enable processing on CPU and GPU accelerators, and the partial reconfiguration of trigger firmware starting from a high level language description (C/C++). The latter capability is enabled by modern High Level Synthesis (HLS) tools, but to what extent this methodology can be applied to perform complex tasks in the L0 trigger, with its stringent latency requirements and the limits imposed by single FPGA resources, is currently being investigated. As a test case for this scenario we considered the online reconstruction of the RICH detector rings on an HLS generated module, using a dedicated primitives data stream with PM hits IDs. Besides, the chosen platform supports the Virtex Ultrascale+ FPGA wide I/O capabilities, allowing for straightforward integration of primitive streams from additional sub-detectors in order to improve the performance of the trigger.https://www.epj-conferences.org/articles/epjconf/pdf/2020/21/epjconf_chep2020_01017.pdf |
| spellingShingle | Ammendola Roberto Biagioni Andrea Ciardiello Andrea Cretaro Paolo Frezza Ottorino Lamanna Gianluca Lo Cicero Francesca Lonardo Alessandro Piandani Roberto Pontisso Luca Salamon Andrea Simula Francesco Soldi Dario Sozzi Marco Vicini Piero L0TP+: the Upgrade of the NA62 Level-0 Trigger Processor EPJ Web of Conferences |
| title | L0TP+: the Upgrade of the NA62 Level-0 Trigger Processor |
| title_full | L0TP+: the Upgrade of the NA62 Level-0 Trigger Processor |
| title_fullStr | L0TP+: the Upgrade of the NA62 Level-0 Trigger Processor |
| title_full_unstemmed | L0TP+: the Upgrade of the NA62 Level-0 Trigger Processor |
| title_short | L0TP+: the Upgrade of the NA62 Level-0 Trigger Processor |
| title_sort | l0tp the upgrade of the na62 level 0 trigger processor |
| url | https://www.epj-conferences.org/articles/epjconf/pdf/2020/21/epjconf_chep2020_01017.pdf |
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