A 6.3-ppm/°C, 100-nA Current Reference With Active Trimming in 28-nm Bulk CMOS Technology

A 6.3-ppm/°C, 100-nA Current Reference With Active Trimming in 28-nm Bulk CMOS Technology

This paper introduces a current reference based on <inline-formula> <tex-math notation="LaTeX">$\Delta V_{GS}$ </tex-math></inline-formula> generation principle and adopts integrated poly-p&#x002B; resistors and a nW-power OTA to reduce the line sensitivity. Imp...

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Bibliographic Details
Main Authors: Andrea Ballo, Alfio Dario Grasso, Marco Privitera
Format: Article
Language:English
Published: IEEE 2022-01-01
Series:IEEE Access
Subjects:
Current reference
low voltage
low power
area-efficient
Internet of Things
sensor nodes
Online Access:https://ieeexplore.ieee.org/document/9916267/
Description
Summary:This paper introduces a current reference based on <inline-formula> <tex-math notation="LaTeX">$\Delta V_{GS}$ </tex-math></inline-formula> generation principle and adopts integrated poly-p&#x002B; resistors and a nW-power OTA to reduce the line sensitivity. Implemented in a 28-nm standard CMOS technology, the circuit provides a nominal current equal to 100nA and operates down to 0.6V with a line sensitivity equal to 1.2&#x0025;/V in the range [0.8-1.8]V and a temperature coefficient equal to 6.3ppm/&#x00B0;C in the range [10-90]&#x00B0;C. Comparison with the state-of-the-art confirms the validity of the proposed solution and its suitability to be exploited in ultra-low-power and area-constrained applications.
ISSN:2169-3536

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